Espressif Systems ESP32 Technical Reference Manual page 102

8.4 Registers
8.4 Registers
31 30
0 1
TIMGn_Tx_EN When set, the timer
TIMGn_Tx_INCREASE When set, the timer
cleared, the timer
TIMGn_Tx_AUTORELOAD When set, timer
TIMGn_Tx_DIVIDER Timer
TIMGn_Tx_EDGE_INT_EN When set, an alarm will generate an edge type interrupt. (R/W)
TIMGn_Tx_LEVEL_INT_EN When set, an alarm will generate a level type interrupt. (R/W)
TIMGn_Tx_ALARM_EN When set, the alarm is enabled. (R/W)
31
TIMGn_TxLO_REG After writing to TIMGn_TxUPDATE_REG, the low 32 bits of the time-base counter
of timer x can be read here. (RO)
31
TIMGn_TxHI_REG After writing to TIMGn_TxUPDATE_REG, the high 32 bits of the time-base counter
of timer x can be read here. (RO)
Espressif Systems
Register 8.1: TIMGn_TxCONFIG_REG (x: 0-1) (0x0+0x24*x)
29 28
1
x time-base counter is enabled. (R/W)
x time-base counter will decrement. (R/W)
x clock (Tx_clk) prescale value. (R/W)
Register 8.2: TIMGn_TxLO_REG (x: 0-1) (0x4+0x24*x)
0x000000000
Register 8.3: TIMGn_TxHI_REG (x: 0-1) (0x8+0x24*x)
0x000000000
0x00001
x time-base counter will increment every clock tick. When
x auto-reload at alarm is enabled. (R/W)
101 ESP32 Technical Reference Manual V1.0
8 64-BIT TIMERS
13 12 11 10
0 0 0 Reset
0
Reset
0
Reset