Espressif Systems ESP32 Technical Reference Manual page 69

5.3 Register Summary
LEDC_DUTY_HSCHn is a fixed-point register with 4 fractional bits. As stated before, LEDC_DUTY_HSCHn[24..4]
is used in the PWM calculation directly, LEDC_DUTY_HSCHn[3..0] can be used to dither the output. If this value
is non-zero, with a statistical chance of LEDC_DUTY_HSCHn[3..0]/16, the actual PWM pulse will be one cycle
longer. This effectively increases the resolution of the PWM generator to 24 bits, but at the cost of a slight jitter in
the duty cycle.
The channels also have ability to automatically fade from one duty cycle value to another. This feature is enabled
by setting LEDC_DUTY_START_HSCHn. When this bit is set, the PWM controller will automatically increment or
decrement the value in LEDC_DUTY_HSCHn, depending on whether the bit
cleared, respectively. The speed the duty cycle changes is defined as such: every
cycles, the content of LEDC_DUTY_SCALE_HSCHn
The length of the fade can be limited by setting LEDC_DUTY_NUM_HSCHn: the fade will only last that number of
cycles before finishing. A finished fade also generates an interrupt.
Figure 13 is an illustration of this. In this configuration, LEDC_DUTY_NUM_HSCHn_R increases by
LEDC_DUTY_SCALE_HSCHn
cycle of the output signal.
5.2.4 Interrupts
• LEDC_DUTY_CHNG_END_LSCHn_INT: Triggered when a fade on a low-speed channel has finished.
• LEDC_DUTY_CHNG_END_HSCHn_INT: Triggered when a fade on a high-speed channel has finished.
• LEDC_HS_TIMERx_OVF_INT: Triggered when a high-speed timer has reached its maximum counter value.
• LEDC_LS_TIMERx_OVF_INT: Triggered when a low-speed timer has reached its maximum counter value.
5.3 Register Summary
Name
Configuration registers
LEDC_CONF_REG
LEDC_HSCH0_CONF0_REG
LEDC_HSCH1_CONF0_REG
LEDC_HSCH2_CONF0_REG
LEDC_HSCH3_CONF0_REG
LEDC_HSCH4_CONF0_REG
LEDC_HSCH5_CONF0_REG
LEDC_HSCH6_CONF0_REG
Espressif Systems
Figure 13: Output Signal Diagram of Gradient Duty Cycle
every LEDC_DUTY_CYCLE_HSCHn
Description
Global ledc configuration register
Configuration register 0 for high-speed channel 0
Configuration register 0 for high-speed channel 1
Configuration register 0 for high-speed channel 2
Configuration register 0 for high-speed channel 3
Configuration register 0 for high-speed channel 4
Configuration register 0 for high-speed channel 5
Configuration register 0 for high-speed channel 6
LEDC_DUTY_INC_HSCHn
is added to or subtracted from LEDC_DUTY_HSCHn[24..4].
clock cycles, which is reflected in the duty
68 ESP32 Technical Reference Manual V1.0
5 LED_PWM
is set or
LEDC_DUTY_CYCLE_HSCHn
Address Access
0x3FF59190 R/W
0x3FF59000 R/W
0x3FF59014 R/W
0x3FF59028 R/W
0x3FF5903C R/W
0x3FF59050 R/W
0x3FF59064 R/W
0x3FF59078 R/W