Espressif Systems ESP32 Technical Reference Manual page 110

9.3 Functional Description
9.3.1.1 Operating Procedure
When a watchdog timer is enabled, it will proceed in loops from stage 0 to stage 3, then back to stage 0 and
start again. The expiry action and time period for each stage can be configured individually.
Every stage can be configured for one of the following actions when the expiry timer reaches the stages timeout
value:
• Trigger an interrupt
When the stage expires an interrupt is triggered.
• Reset a CPU core
When the stage expires the designated CPU core will be reset. MWDT0 CPU reset only resets the PRO
CPU. MWDT1 CPU reset only resets the APP CPU. The RWDT CPU reset can reset either or both or none
depending on configuration.
• Reset the main system
When the stage expires, the main system, including the MWDTs, will be reset. In this article, main system
refers to CPU and all peripherals. The RTC is an exception to this and it will not be reset.
• Reset the main system and RTC
When the stage expires the main system and the RTC will both be reset. This action is only available in the
RWDT.
• Disabled
This stage will have no effects on the system.
When software feeds the the watchdog timer, it returns to stage 0 and its expiry counter restarts from 0.
9.3.1.2 Write Protection
Both the MWDTs as well as the RWDT can be protected from accidental writing. To accomplish this, they have a
write-key register (TIMERS_WDT_WKEY for the MWDT, RTC_CNTL_WDT_WKEY for the RWDT.) On reset, these
registers are initialized to the value 0x50D83AA1. When the value in this register is changed from 0x50D83AA1,
write protection is enabled. Writes to any WDT register, including the feeding register (but excluding the write-key
register itself), are ignored. The recommended procedure for accessing a WDT is:
1. Disable the write protection
2. Make the required modification or feed the watchdog
3. Re-enable the write protection
9.3.1.3 Flash Boot Protection
During flash booting, the MWDT in timer group 0 (TIMG0) as well as the RWDT are automatically enabled. Stage
0 for the enabled MWDT is automatically configured to reset the system upon expiry; stage 0 for the RWDT resets
the RTC when it expires. After booting, the register TIMERS_WDT_FLASHBOOT_MOD_EN should be cleared to
stop the flash boot protection procedure for the MWDT, and RTC_CNTL_WDT_FLASHBOOT_MOD_EN should
be cleared to do the same for the RWDT. After this, the MWDT and RWDT can be configured by software.
Espressif Systems 109 ESP32 Technical Reference Manual V1.0
9 WATCHDOG TIMERS