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6 I/O PORTS (PPORT)
Make sure the Pxy port interrupt is disabled before altering the PCLK register and PxCHATEN.PxCHATENy
bit settings. A Pxy port interrupt may erroneously occur if these settings are altered in an interrupt enabled sta-
tus. Furthermore, enable the interrupt after a lapse of four or more CLK_PPORT cycles from enabling the chat-
tering filter function.
If the clock generator is configured so that it will supply CLK_PPORT to PPORT in SLEEP mode, the chatter-
ing filter of the port will function even in SLEEP mode. If CLK_PPORT is configured to stop in SLEEP mode,
PPORT inactivates the chattering filter during SLEEP mode to input pin status transitions directly to itself.
Key-entry reset function
This function issues a reset request when low-level pulses are input to all the specified ports simultaneously.
Make the following settings when using this function:
1. Configure the ports to be used for key-entry reset as general-purpose input ports (refer to "Initial settings
when using a port as a general-purpose input port (only for the ports with GPIO function)").
2. Configure the input pin combination for key-entry reset using the PCLK.KRSTCFG[1:0] bits.
Note: When enabling the key-entry reset function, be sure to configure the port pins to be used for it
as general-purpose input pins before setting the PCLK.KRSTCFG[1:0] bits.
PPORT issues a reset request immediately after all the input pins specified by the PCLK.KRSTCFG[1:0] are
set to a low level if the chattering filter function is disabled (initial status). To issue a reset request only when
low-level signals longer than the time configured are input, enable the chattering filter function for all the ports
used for key-entry reset.
The pins configured for key-entry reset can also be used as general-purpose input pins.
6.5 Interrupts
When the GPIO function is selected for the port with an interrupt function, the port input interrupt function can be
used.
Interrupt
Port input interrupt
PxINTF.PxIFy
PINTFGRP.PxINT
Interrupt edge selection
Port input interrupts will occur at the falling edge of the input signal when setting the PxINTCTL.PxEDGEy bit
to 1, or the rising edge when setting to 0.
Interrupt enable
PPORT provides interrupt enable bits (PxINTCTL.PxIEy bit) corresponding to each interrupt flag. An inter-
rupt request is sent to the interrupt controller only when the interrupt flag, of which interrupt has been enabled
by the interrupt enable bit, is set. For more information on interrupt control, refer to the "Interrupt Controller"
chapter.
Interrupt check in port group unit
When interrupts are enabled in two or more port groups, check the PINTFGRP.PxINT bit in the interrupt han-
dler first. It helps minimize the handler codes for finding the port that has generated an interrupt. If this bit is
set to 1, an interrupt has occurred in the port group. Next, check the PxINTF.PxIFy bit set to 1 in the port group
to determine the port that has generated an interrupt. Clearing the PxINTF.PxIFy bit also clears the PINTFGRP.
PxINT bit. If the port is set to interrupt disabled status by the PxINTCTL.PxIEy bit, the PINTFGRP.PxINT bit
will not be set even if the PxINTF.PxIFy bit is set to 1.
6-6
Table 6.5.1 Port Input Interrupt Function
Interrupt flag
Rising or falling edge of the input signal
Setting an interrupt flag in the port group
Seiko Epson Corporation
Set condition
S1C17M12/M13 TECHNICAL MANUAL
Clear condition
Writing 1
Clearing PxINTF.PxIFy
(Rev. 1.2)
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