Uart3 Ch.n Status And Interrupt Flag Register - Epson S1C17M12 Technical Manual

UART3 Ch.n Status and Interrupt Flag Register

Register name Bit
UAnINTF 15–10 –
9
8
7
6
5
4
3
2
1
0
Bits 15–10 Reserved
Bit 9 RBSY
This bit indicates the receiving status. (See Figure 11.5.3.1.)
1 (R): During receiving
0 (R): Idle
Bit 8 TBSY
This bit indicates the sending status. (See Figure 11.5.2.1.)
1 (R): During sending
0 (R): Idle
Bit 7 Reserved
Bit 6 TENDIF
Bit 5 FEIF
Bit 4 PEIF
Bit 3 OEIF
Bit 2 RB2FIF
Bit 1 RB1FIF
Bit 0 TBEIF
These bits indicate the UART3 interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
The following shows the correspondence between the bit and interrupt:
UAnINTF.TENDIF bit: End-of-transmission interrupt
UAnINTF.FEIF bit:
UAnINTF.PEIF bit:
UAnINTF.OEIF bit:
UAnINTF.RB2FIF bit: Receive buffer two bytes full interrupt
UAnINTF.RB1FIF bit: Receive buffer one byte full interrupt
UAnINTF.TBEIF bit:
S1C17M12/M13 TECHNICAL MANUAL
(Rev. 1.2)
Bit name Initial
0x00
RBSY 0
TBSY 0
– 0
TENDIF 0
FEIF 0
PEIF 0
OEIF 0
RB2FIF 0
RB1FIF 0
TBEIF 1
Framing error interrupt
Parity error interrupt
Overrun error interrupt
Transmit buffer empty interrupt
Seiko Epson Corporation
Reset R/W
– R –
H0/S0 R
H0/S0 R
– R
H0/S0 R/W Cleared by writing 1.
H0/S0 R/W Cleared by writing 1 or reading the
UAnRXD register.
H0/S0 R/W
H0/S0 R/W Cleared by writing 1.
H0/S0 R Cleared by reading the UAnRXD reg-
ister.
H0/S0 R
H0/S0 R Cleared by writing to the UAnTXD
register.
11 UART (UART3)
Remarks
11-13