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1.2 Block Diagram
DCLK
DSIO
DST2
System clock
Clock generator
(CLG)
IOSC
FOUT
oscillator
OSC3
OSC3
oscillator
OSC4
EXOSC
EXOSC
input circuit
System reset controller
(SRC)
Power-on reset
(POR)
#RESET
Brownout reset
(BOR)
V
DD
V
DD2
Power generator
V
D1
(PWG)
V
SS
V
SS2
S1C17M12/M13 TECHNICAL MANUAL
(Rev. 1.2)
CPU core & debugger
(S1C17)
Interrupt request
16-bit internal bus
Interrupt signal
Interrupt
controller
(ITC)
I/O port
(PPORT)
Watchdog timer
(WDT2)
Supply voltage
detector
(SVD3)
16-bit timer
(T16)
4 Ch.
16-bit PWM timer
(T16B)
1 Ch.
Figure 1.2.1 S1C17M12/M13 Block Diagram
Seiko Epson Corporation
Multiplier/divider
Coprocessor bus
(COPRO2)
Internal RAM
32-bit RAM bus
2K bytes
Flash memory
Instruction bus
16K bytes
P00–07
P10–17
P20–24
P40–47
P50–54
PD0–D1
PD3–D4
PD2
EXSVD0–1
TOUT00–01
CAP00–01
EXCL00–01
1 OVERVIEW
V
PP
UART
USIN0
(UART3)
USOUT0
1 Ch.
Synchronous
SDI0–1
serial interface
SDO0–1
(SPIA)
SPICLK0–1
2 Ch.
#SPISS0–1
I
2
C
SDA0
(I2C)
SCL0
1 Ch.
IR remote
controller
REMO
(REMC2)
CLPLS
1 Ch.
Seven-segment
COM0–4
LED controller
SEG0–7
(LEDC)
12-bit A/D
ADIN00–07
converter
#ADTRG0
(ADC12A)
VREFA0
1 Ch.
* Not available in the S1C17M12.
∗
1-3
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