Spia Ch.n Interrupt Enable Register - Epson S1C17M12 Technical Manual

12 SYNCHRONOUS SERIAL INTERFACE (SPIA)
Bits 15–8 Reserved
Bit 7 BSY
This bit indicates the SPIA operating status.
1 (R): Transmit/receive busy (master mode), #SPISSn = Low level (slave mode)
0 (R): Idle
Bits 6–4 Reserved
Bit 3 OEIF
Bit 2 TENDIF
Bit 1 RBFIF
Bit 0 TBEIF
These bits indicate the SPIA interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag (OEIF, TENDIF)
0 (W): Ineffective
The following shows the correspondence between the bit and interrupt:
SPInINTF.OEIF bit:
SPInINTF.TENDIF bit: End-of-transmission interrupt
SPInINTF.RBFIF bit:
SPInINTF.TBEIF bit:

SPIA Ch.n Interrupt Enable Register

Register name Bit
SPInINTE 15–8 –
7–4 –
3
2
1
0
Bits 15–4 Reserved
Bit 3 OEIE
Bit 2 TENDIE
Bit 1 RBFIE
Bit 0 TBEIE
These bits enable SPIA interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
The following shows the correspondence between the bit and interrupt:
SPInINTE.OEIE bit:
SPInINTE.TENDIE bit: End-of-transmission interrupt
SPInINTE.RBFIE bit: Receive buffer full interrupt
SPInINTE.TBEIE bit: Transmit buffer empty interrupt
12-14
Overrun error interrupt
Receive buffer full interrupt
Transmit buffer empty interrupt
Bit name Initial
0x00
0x0
OEIE 0
TENDIE 0
RBFIE 0
TBEIE 0
Overrun error interrupt
Seiko Epson Corporation
Reset R/W
– R –
– R
H0 R/W
H0 R/W
H0 R/W
H0 R/W
S1C17M12/M13 TECHNICAL MANUAL
Remarks
(Rev. 1.2)