Epson S1C17M12 Technical Manual page 241

Address Register name
0x5278 SPI1INTF
(SPIA Ch.1 Interrupt
Flag Register)
0x527a SPI1INTE
(SPIA Ch.1 Interrupt
Enable Register)
0x5320–0x5332
Address Register name
0x5320 REMCLK
(REMC2 Clock Con-
trol Register)
0x5322 REMDBCTL
(REMC2 Data Bit
Counter Control
Register)
0x5324 REMDBCNT
(REMC2 Data Bit
Counter Register)
0x5326 REMAPLEN
(REMC2 Data Bit
Active Pulse Length
Register)
0x5328 REMDBLEN
(REMC2 Data Bit
Length Register)
0x532a REMINTF
(REMC2 Status
and Interrupt Flag
Register)
0x532c REMINTE
(REMC2 Interrupt
Enable Register)
0x5330 REMCARR
(REMC2 Carrier
Waveform Register)
S1C17M12/M13 TECHNICAL MANUAL
(Rev. 1.2)
APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS
Bit Bit name
15–8 –
7 BSY
6–4 –
3 OEIF
2 TENDIF
1 RBFIF
0 TBEIF
15–8 –
7–4 –
3 OEIE
2 TENDIE
1 RBFIE
0 TBEIE
Bit Bit name
15–9 –
8 DBRUN
7–4 CLKDIV[3:0]
3–2 –
1–0 CLKSRC[1:0]
15–10 –
9 PRESET
8 PRUN
7–5 –
4 REMOINV
3 BUFEN
2 TRMD
1 REMCRST
0 MODEN
15–0 DBCNT[15:0]
15–0 APLEN[15:0]
15–0 DBLEN[15:0]
15–11 –
10 DBCNTRUN
9 DBLENBSY
8 APLENBSY
7–2 –
1 DBIF
0 APIF
15–8 –
7–2 –
1 DBIE
0 APIE
15–8 CRDTY[7:0]
7–0 CRPER[7:0]
Seiko Epson Corporation
Initial Reset R/W
0x00 – R
0 H0 R
0x0 – R
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R
1 H0/S0 R
0x00 – R
0x0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
IR Remote Controller (REMC2)
Initial Reset R/W
0x00 – R
0 H0 R/W
0x0 H0 R/W
0x0 – R
0x0 H0 R/W
0x00 – R
0 H0/S0 R/W
0 H0/S0 R/W
0x0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 W
0 H0 R/W
0x0000 H0/S0 R
0x0000 H0 R/W
0x0000 H0 R/W
0x00 – R
0 H0/S0 R
0 H0 R
0 H0 R
0x00 – R
0 H0/S0 R/W
0 H0/S0 R/W
0x00 – R
0x00 – R
0 H0 R/W
0 H0 R/W
0x00 H0 R/W
0x00 H0 R/W
Remarks
–
Cleared by writing 1.
Cleared by reading the
SPI1RXD register.
Cleared by writing to the
SPI1TXD register.
–
Remarks
–
–
Cleared by writing 1 to the
REMDBCTL.REMCRST bit.
–
Cleared by writing 1 to the
REMDBCTL.REMCRST bit.
Writing enabled when REM-
DBCTL.MODEN bit = 1.
Writing enabled when REM-
DBCTL.MODEN bit = 1.
–
Cleared by writing 1 to the
REMDBCTL.REMCRST bit.
Effective when the REM-
DBCTL.BUFEN bit = 1.
–
Cleared by writing 1 to this
bit or the REMDBCTL.REM-
CRST bit.
–
–
AP-A-15