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16 SEVEN-SEGMENT LED CONTROLLER (LEDC)
LEDC Lighting Period Setting Register
Register name
Bit
LEDCLPSET
15–8 –
7–0 LICLKDIV[7:0]
Bits 15–8 Reserved
Bits 7–0
LICLKDIV[7:0]
These bits set a CLK_LEDC division ratio to determine the COM lighting period. For more informa-
tion, refer to "LED Lighting Cycle."
LEDC Interrupt Flag Register
Register name
Bit
LEDCINTF
15–8 –
7–1 –
0
Bits 15–1 Reserved
Bit 0
COM0LTIF
This bit indicates the COM0 lighting interrupt cause occurrence status.
1 (R):
Cause of interrupt occurred
0 (R):
No cause of interrupt occurred
1 (W):
Clear flag
0 (W):
Ineffective
LEDC Interrupt Enable Register
Register name
Bit
LEDCINTE
15–8 –
7–1 –
0
Bits 15–1 Reserved
Bit 0
FRMIE
This bit enables the COM0 lighting interrupt.
1 (R/W): Enable interrupt
0 (R/W): Disable interrupt
LEDC COMxy Data Registers
Register name
Bit
LEDCDATxy
15–8 COMy[7:0]
7–0 COMx[7:0]
Bits 15–8 COMy[7:0]
These bits are SEG data to display during the COMy lighting period.
Bits 7–0
COMx[7:0]
These bits are SEG data to display during the COMx lighting period.
For the correspondence between the bits and segments, refer to "Display Data Registers."
The number of COMs that can be used and the configuration of the LEDCDATAxy registers
depend on the model. Furthermore, settings up to the COM number that has been specified with the
LEDCCTL.NDIGITS[2:0] bits are only effective.
16-8
Bit name
Initial
0x00
0xff
Bit name
Initial
0x00
0x00
COM0LTIF
0
Bit name
Initial
0x00
0x00
COM0LTIE
0
Bit name
Initial
0x00
0x00
Seiko Epson Corporation
Reset
R/W
–
R
–
H0
R/W
Reset
R/W
–
R
–
–
R
H0
R/W
Cleared by writing 1.
Reset
R/W
–
R
–
–
R
H0
R/W
Reset
R/W
H0
R/W
–
H0
R/W
S1C17M12/M13 TECHNICAL MANUAL
Remarks
Remarks
Remarks
Remarks
xy = 10, 32, 54, 76
(Rev. 1.2)
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