Table of Contents
Advertisement
11.6.3 Overrun Error
If the receive data buffer is still full (two bytes of received data have not been read) when a data reception to the
shift register has completed, an overrun error occurs as the data cannot be transferred to the receive data buffer.
When an overrun error occurs, the UAnINTF.OEIF bit (overrun error interrupt flag) is set to 1.
11.7 Interrupts
The UART3 has a function to generate the interrupts shown in Table 11.7.1.
Interrupt
End of transmission
Framing error
Parity error
Overrun error
Receive buffer two bytes full UAnINTF.RB2FIF When the second received data byte is
Receive buffer one byte full UAnINTF.RB1FIF When the first received data byte is load-
Transmit buffer empty
The UART3 provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the
interrupt controller only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is
set. For more information on interrupt control, refer to the "Interrupt Controller" chapter.
11.8 Control Registers
UART3 Ch.n Clock Control Register
Register name
Bit
UAnCLK
15–9 –
8
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
Bits 15–9 Reserved
Bit 8
DBRUN
This bit sets whether the UART3 operating clock is supplied in DEBUG mode or not.
1 (R/W): Clock supplied in DEBUG mode
0 (R/W): No clock supplied in DEBUG mode
Bits 7–6
Reserved
Bits 5–4
CLKDIV[1:0]
These bits select the division ratio of the UART3 operating clock.
Bits 3–2
Reserved
S1C17M12/M13 TECHNICAL MANUAL
(Rev. 1.2)
Table 11.7.1 UART3 Interrupt Function
Interrupt flag
UAnINTF.TENDIF When the UAnINTF.TBEIF bit = 1 after
the stop bit has been sent
UAnINTF.FEIF
Refer to the "Receive Errors."
UAnINTF.PEIF
Refer to the "Receive Errors."
UAnINTF.OEIF
Refer to the "Receive Errors."
loaded to the receive data buffer in which
the first byte is already received
ed to the emptied receive data buffer
UAnINTF.TBEIF
When transmit data written to the trans-
mit data buffer is transferred to the shift
register
Bit name
Initial
0x00
DBRUN
0
0x0
0x0
0x0
0x0
Seiko Epson Corporation
Set condition
Reset
R/W
–
R
–
H0
R/W
–
R
H0
R/W
–
R
H0
R/W
11 UART (UART3)
Clear condition
Writing 1 or software reset
Writing 1, reading received
data that encountered an
error, or software reset
Writing 1, reading received
data that encountered an
error, or software reset
Writing 1 or software reset
Reading received data or
software reset
Reading data to empty
the receive data buffer or
software reset
Writing transmit data
Remarks
11-9
Advertisement
Table of Contents
