NEC mPD178054 Series User Manual page 217

A/D converter
Interrupt
PLL frequency synthesizer
Frequency counter
Power-on clear
Notes 1. Undefined only at power-on clear reset
2. 03H only at power-on clear reset
CHAPTER 16 RESET FUNCTION
Table 16-1. Hardware Status After Reset (2/2)
Hardware
Mode register 3 (ADM3)
A/D conversion result register 3 (ADCR3)
Analog input channel specification register 3 (ADS3)
Power-fail comparison mode register 3 (PFM3)
Power-fail comparison threshold value register 3 (PFT3)
Request flag registers (IF0L and IF0H)
Mask flag registers (MK0L and MK0H)
Priority specification flag registers (PR0L and PR0H)
External interrupt rising edge enable register (EGP)
External interrupt falling edge enable register (EGN)
PLL mode select register (PLLMD)
PLL reference mode register (PLLRF)
PLL unlock F/F judge register (PLLUL)
PLL data registers (PLLRH, PLLRL, and PLLR0)
PLL data transfer register (PLLNS)
IF counter mode select register (IFCMD)
IF counter gate judge register (IFCJG)
IF counter control register (IFCCR)
IF counter register (IFCR)
POC status register (POCS)
User's Manual U15104EJ2V0UD
Status After Reset
00H
Undefined
00H
00H
00H
00H
FFH
FFH
00H
00H
00H
0FH
Note 1
Retained
Undefined
00H
00H
00H
00H
0000H
Note 2
Retained
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