(3) Priority specification flag registers (PR0L, PR0H)
The priority specification flags are used to set the corresponding maskable interrupt priority orders.
PR0L and PR0H are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are used
as a 16-bit register PR0, use a 16-bit memory manipulation instruction for the setting.
Reset input sets these registers to FFH.
Figure 12-4. Format of Priority Specification Flag Registers (PR0L, PR0H)
Symbol
<7>
<6>
PR0L
CSIPR31
KYPR
<7>
<6>
PR0H
TMPR53
TMPR52
××PR×
0
High priority level
1
Low priority level
Caution When the watchdog timer is used in watchdog timer mode 1, set the WDTPR flag to 1.
CHAPTER 12 INTERRUPT FUNCTIONS
<5>
<4>
<3>
<2>
PPR4
PPR3
PPR2
PPR1
<5>
<4>
<3>
<2>
TMPR51
TMPR50
CSIPR30
CSIPR32
Priority level selection
User's Manual U15104EJ2V0UD
Address
<1>
<0>
PPR0
WDTPR
FFE8H
<1>
<0>
ADPR
BTMPR0
FFE9H
After reset
R/W
FFH
R/W
FFH
R/W
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