NEC mPD178054 Series User Manual page 191

CHAPTER 13 PLL FREQUENCY SYNTHESIZER
Because the least significant bit of the division value N must be set to bit 7 (PLLSCN) of PLL data register
0 (PLLR0), data must be set by shifting the result of the above calculation 1 bit to the right.
Data is set to the PLL data registers (PLLR and PLLR0) as follows.
Result of calculation (N value)
0 0 0 0 1 0 1 0
0 A
Shifted 1 bit to right
Value shifted 1 bit to right
0 0 0 0 0 1 0 1
0 5
PLLR
PLLRH
b7 b6 b5 b4 b3 b2 b1 b0
b16 b15 b14 b13 b12 b11 b10 b9
Programmable counter value
0 0 0 0 0 1 0 1
0 5
After setting the above PLL data registers (PLLR and PLLR0), data must be transferred to the
programmable counter and swallow counter by setting bit 0 (PLLNS0) of the PLL data transfer register
(PLLNS).
In this example, a value of half the N value is set to the high-order 16 bits of the PLL data register (PLLR)
by shifting the N value resulting from calculation 1 bit to the right.
If the N value is calculated as follows with the least significant bit of the N value in PLLSCN fixed to 0,
the result of the calculation (N
If the calculation result is set in this way, however, the input frequency (f
of the set value N .
PLLR
f
VCOL
N =
PLLR
2f
r
0 0 1 0 0 0 1 1
2 3
0 0 0 1 0 0 0 1
1 1
PLLRL
b7 b6 b5 b4 b3 b2 b1 b0
b8 b7 b6 b5 b4 b3 b2 b1
Swallow counter value
0 0 0 1 0 0 0 1
1 1
) can be set to the PLL data register (PLLR) as is.
PLLR
User's Manual U15104EJ2V0UD
H
0
H
PLLR0
PLLSCN
b7 b6 b5 b4 b3 b2 b1 b0
b0
Fixed to 0
0
0
) is 2 × f
(reference frequency)
VCOL r
191