NEC mPD178054 Series User Manual page 141

(2) Power-fail comparison mode
In the power-fail comparison mode, the digital value converted from analog input is compared in units of 8
bits.
If the result of the comparison matches the condition set by bit 6 (PFCM3) of power-fail comparison mode
register 3 (PFM3), an interrupt request (INTAD3) is generated.
Moreover, the power-fail comparison mode can be used in the HALT mode. At this time, the HALT mode can
be released by generating the interrupt request signal (INTAD3) as a result of comparison (however, the A/
D operation must be executed before the HALT instruction is executed).
To set the power-fail comparison mode, set bit 7 (PEEN3) of PFM3 to 1, set bit 6 (PFCM3) to the generation
condition of INTAD, and assign the threshold value to be compared with the value of A/D conversion result
register 3 (ADCR3) to power-fail comparison threshold value register 3 (PFT3).
By setting bit 7 (ADCS3) of A/D converter mode register 3 (ADM3) to 1, the voltage applied to the analog input
pin specified by ADS3 is converted into a digital signal. When the A/D conversion has been completed, the
result of the conversion is stored in ADCR3. This conversion result is compared with the value set in PFT3
and if the result of the comparison matches the condition set by bit 6 (PFCM3) of PFM3, an interrupt request
signal (INTAD3) is generated.
Figure 10-8. Power-Fail Comparison Threshold Value Register 3 (PFT3)
Symbol 7 6
PFT3 PFT37 PFT36
Remark Bit 7 (PFT37) is the MSB, and bit 0 (PFT30) is the LSB.
For the setting value, refer to 10.4.2 Input voltage and conversion results.
Cautions 1. In the power-fail comparison mode, the first result (A/D conversion result and interrupt
request (INTAD)) of the A/D conversion (started by setting bit 7 (ADCS3) of A/D converter
mode register 3 (ADM3) to 1) is not correct.
2. When executing A/D conversion in the HALT mode using the power-fail HALT repeat
mode, clear the interrupt request flag (ADIF) after the first conversion has been completed
immediately after bit 7 (ADCS3) of ADM3 has been set to 1, and bit 5 (PFHRM3) of power-
fail comparison mode register 3 (PFM3) has been set to 1, before executing the HALT
instruction.
3. To set the power-fail comparison mode in the HALT mode, be sure to set bit 5 (PFHRM3)
of PFM3 to 1 before executing the HALT instruction; otherwise comparison cannot be
performed correctly because the conversion result in the HALT mode is not stored in A/
D conversion result register 3 (ADCR3). If bit 5 (PFHRM3) of PFM3 is set in the normal
operating mode (other than HALT mode), the A/D conversion is not performed correctly.
Therefore, be sure to clear this bit to 0 in the normal mode.
CHAPTER 10 A/D CONVERTER
5 4 3
PFT35 PFT34 PFT33 PFT32
User's Manual U15104EJ2V0UD
2 1 0 Address
PFT31 PFT30 FF15H
After reset R/W
00H R/W
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