Chapter 13 Pll Frequency Synthesizer; Function Of Pll Frequency Synthesizer - NEC mPD178054 Series User Manual

13.1 Function of PLL Frequency Synthesizer

The PLL (Phase Locked Loop) frequency synthesizer is used to lock the frequency in the MF (Middle Frequency),
HF (High Frequency), and VHF (Very High Frequency) ranges to a specific frequency by means of phase difference
comparison.
The PLL frequency synthesizer divides the frequency of the signal input from the VCOL or VCOH pin by using
a programmable divider, and outputs the phase difference between the frequency of this signal and reference
frequency from the EO0 and EO1 pin.
The following input pin states and frequency division modes are used.
(1) Direct division (MF) mode
The VCOL pin is used.
The VCOH pin is set in the status specified by bit 3 (VCOHDMD) of the PLL mode select register (PLLMD).
(2) Pulse swallow (HF) mode
The VCOL pin is used.
The VCOH pin is set in the status specified by bit 3 (VCOHDMD) of PLLMD.
(3) Pulse swallow (VHF) mode
The VCOH pin is used.
The VCOL pin is set in the status specified by bit 2 (VCOLDMD) of PLLMD.
(4) VCOL and VCOH pin disable
The VCOL and VCOH pins are set in the status specified by bits 2 (VCOLDMD) and 3 (VCOHDMD) of PLLMD.
At this time, the phase comparator, reference frequency generator, and charge pump operate.
(5) PLL disable
The PLL disabled status is set by the PLL reference mode register (PLLRF).
The VCOH and VCOL pins are set in the status specified by bits 2 (VCOLDMD) and 3 (VCOHDMD) of PLLMD.
The EO0 and EO1 pins go into a high-impedance state.
At this time, all the internal PLL operations are stopped.
These division modes are selected by using the PLL mode select register (PLLMD).
The division value (N value) is set to the programmable divider by using the PLL data register. Frequency division
in each of the above modes is carried out according to the value (N value) set to the programmable divider.
Table 13-1 shows the division modes, input pins used (VCOL pin or VCOH pin), and the value that can be set to
the programmable divider.

CHAPTER 13 PLL FREQUENCY SYNTHESIZER

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