Configuration Of Pll Frequency Synthesizer - NEC mPD178054 Series User Manual

13.2 Configuration of PLL Frequency Synthesizer

The PLL frequency synthesizer consists of the following hardware.
Table 13-2. Configuration of PLL Frequency Synthesizer
Figure 13-1. Block Diagram of PLL Frequency Synthesizer
PLL mode
select register
(PLLMD)
VCOH
VCOL
DMD DMD
VCOH
Mixer
VCOL
Note
Voltage
control
generator
Note
Lowpass
filter
Note External circuit
CHAPTER 13 PLL FREQUENCY SYNTHESIZER
Item
Data registers PLL data register L (PLLRL)
PLL data register H (PLLRH)
PLL data register 0 (PLLR0)
Control registers PLL mode select register (PLLMD)
PLL reference mode register (PLLRF)
PLL unlock F/F judge register (PLLUL)
PLL data transfer register (PLLNS)
PLL data register
PLL PLL
(PLLRL, PLLRH, PLLR0)
MD1 MD0
2 2
Input select Programmable
block
divider
Reference
frequency
4.5 MHz
generator
4
PLL PLL PLL
RF3 RF2 RF1
PLL reference
mode register
(PLLRF)
User's Manual U15104EJ2V0UD
Configuration
Internal bus
PLL
data transfer
register (PLLNS)
PLL
NS0
f
N
Phase
comparator
φ
( -DET)
f
r
Unlock
FF
PLL PLL
RF0 UL0
PLL unlock
F/F judge register
(PLLUL)
Internal bus
EO1
Charge
pump
EO0
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