NEC mPD178054 Series User Manual page 15

Figure No.
2-1 Pin I/O Circuits ....................................................................................................................................
Memory Map of µ PD178053 ..............................................................................................................
3-1
Memory Map of µ PD178054 ..............................................................................................................
3-2
Memory Map of µ PD178F054 ............................................................................................................
3-3
Data Memory Addressing of µ PD178053 ..........................................................................................
3-4
Data Memory Addressing of µ PD178054 ..........................................................................................
3-5
Data Memory Addressing of µ PD178F054 ........................................................................................
3-6
3-7 Configuration of Program Counter .....................................................................................................
3-8 Configuration of Program Status Word ..............................................................................................
3-9 Configuration of Stack Pointer ...........................................................................................................
3-10 Data to Be Saved to Stack Memory ...................................................................................................
3-11 Data to Be Restored from Stack Memory ..........................................................................................
3-12 Configuration of General-Purpose Register ......................................................................................
4-1 Port Types ...........................................................................................................................................
4-2 Block Diagram of P00 to P04 .............................................................................................................
4-3 Block Diagram of P05 and P06 ..........................................................................................................
4-4 Block Diagram of P10 to P15 .............................................................................................................
4-5 Block Diagram of P30 to P32 and P35 ..............................................................................................
4-6 Block Diagram of P33 and P34 ..........................................................................................................
4-7 Block Diagram of P36 and P37 ..........................................................................................................
4-8 Block Diagram of P40 to P47 .............................................................................................................
4-9 Block Diagram of Key Input Detector ................................................................................................
4-10 Block Diagram of P50 to P57 .............................................................................................................
4-11 Block Diagram of P60 to P67 .............................................................................................................
4-12 Block Diagram of P70, P74, and P77 ................................................................................................
4-13 Block Diagram of P71 and P75 ..........................................................................................................
4-14 Block Diagram of P72 and P76 ..........................................................................................................
4-15 Block Diagram of P73 .........................................................................................................................
4-16 Block Diagram of P120 and P123 ......................................................................................................
4-17 Block Diagram of P121 and P124 ......................................................................................................
4-18 Block Diagram of P122 and P125 ......................................................................................................
4-19 Block Diagram of P130 to P132 .........................................................................................................
4-20 Format of Port Mode Registers ..........................................................................................................
4-21 Format of Pull-up Resistor Option Register 4 (PU4) .........................................................................
5-1 Format of DTS System Clock Select Register (DTSCK) ..................................................................
5-2 Block Diagram of Clock Generator ....................................................................................................
5-3 Format of Processor Clock Control Register (PCC) .........................................................................
5-4 External Circuit of System Clock Oscillator .......................................................................................
5-5 Examples of Incorrect Resonator Connection ...................................................................................
LIST OF FIGURES (1/4)
Title
User's Manual U15104EJ2V0UD
Page
36
39
40
41
44
45
46
47
47
49
49
49
51
68
70
71
71
72
73
73
74
75
75
76
77
78
78
79
80
81
81
82
85
86
88
89
90
91
92
15