Operation To Set N Value Of Pll Frequency Synthesizer - NEC mPD178054 Series User Manual

(5) Operation of unlock F/F
The unlock F/F detects the unlock status of the PLL frequency synthesizer.
The unlock status of the PLL frequency synthesizer is detected from the up request signal UP and down request
signal DW of the phase comparator ( φ -DET).
Because either of the up request or down request signal outputs a low level in the unlock status, the unlock
status can be detected by using this low-level signal.
The status of the unlock F/F is detected by bit 0 (PLLUL0) of the PLL unlock F/F judge register (PLLUL).
The unlock F/F is set at the cycle of reference frequency f
The PLL unlock F/F judge register is reset when its contents have been read.
To read the PLLUL, therefore, it must be read at a cycle longer than the cycle (1/f

13.4.2 Operation to set N value of PLL frequency synthesizer

The division value (N value) is set to the programmable counter (12 bits) and swallow counter (5 bits) by the PLL
data registers (PLLRL, PLLRH, and PLLR0).
When the N value has been transferred to the programmable counter and swallow counter by bit 0 (PLLNS0) of
the PLL data transfer register (PLLNS), frequency division is carried out in the selected division mode.
Examples of setting the N value in the respective division modes (MF, HF, and VHF) are shown below.
(1) Direct division mode (MF)
(a) Calculating division value N (value set to PLL data register)
f
VCOL
N =
f
r
where,
(b) Example of setting PLL data register
An example of setting the PLL data register to receive broadcasting stations in the following MW band
is shown below.
Receive frequency:
Reference frequency:
Intermediate frequency: 450 kHz
Division value N is calculated as follows:
f
VCOL
N =
f
r
CHAPTER 13 PLL FREQUENCY SYNTHESIZER
f : Input frequency of V
VCOL
f : Reference frequency
r
1422 kHz (MW band)
9 kHz
1422 + 450
= = 208 (decimal)
9
= 0D0H (hexadecimal)
User's Manual U15104EJ2V0UD
selected at that time.
r
pin
COL
) of the reference frequency.
r
189