Table Of Contents - NEC mPD178054 Series User Manual

CHAPTER 1 OUTLINE .......................................................................................................................
1.1 Features..............................................................................................................................
1.2 Applications .......................................................................................................................
1.3 Ordering Information ........................................................................................................
1.4 Pin Configuration (Top View) ..........................................................................................
1.5 Development of 8-Bit DTS Series ...................................................................................
1.6 Block Diagram ...................................................................................................................
1.7 Functional Outline ............................................................................................................
CHAPTER 2 PIN FUNCTION .............................................................................................................
2.1 Pin Function List ...............................................................................................................
2.2 Description of Pin Functions ..........................................................................................
2.2.1 P00 to P06 (Port 0) ..............................................................................................................
2.2.2 P10 to P15 (Port 1) ..............................................................................................................
2.2.3 P30 to P37 (Port 3) ..............................................................................................................
2.2.4 P40 to P47 (Port 4) ..............................................................................................................
2.2.5 P50 to P57 (Port 5) ..............................................................................................................
2.2.6 P60 to P67 (Port 6) ..............................................................................................................
2.2.7 P70 to P77 (Port 7) ..............................................................................................................
2.2.8 P120 to P125 (Port 12) ........................................................................................................
2.2.9 P130 to P132 (Port 13) ........................................................................................................
2.2.10 EO0, EO1 ..............................................................................................................................
2.2.11 VCOL, VCOH ........................................................................................................................
2.2.12 AMIFC ...................................................................................................................................
2.2.13 FMIFC ...................................................................................................................................
2.2.14 RESET ..................................................................................................................................
2.2.15 X1, X2 ...................................................................................................................................
2.2.16 REGOSC ...............................................................................................................................
2.2.17 REGCPU ...............................................................................................................................
2.2.18 V .........................................................................................................................................
DD
2.2.19 GND ......................................................................................................................................
2.2.20 V PORT ..............................................................................................................................
DD
2.2.21 GNDPORT ............................................................................................................................
2.2.22 V PLL ..................................................................................................................................
DD
2.2.23 GNDPLL ................................................................................................................................
( µ PD178F054 only) .......................................................................................................
2.2.24 V
PP
2.2.25 IC (Mask ROM version only) ................................................................................................
2.3 Pin I/O Circuits and Recommended Connections of Unused Pins ...........................
CHAPTER 3 CPU ARCHITECTURE .................................................................................................
3.1 Memory Space ...................................................................................................................
3.1.1 Internal program memory space ..........................................................................................
3.1.2 Internal data memory space ................................................................................................
3.1.3 Special Function Register (SFR) area .................................................................................
3.1.4 Data memory addressing .....................................................................................................
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User's Manual U15104EJ2V0UD
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