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(2) PLL reference mode register (PLLRF)
This register selects the reference frequency f
of the PLL frequency synthesizer.
PLLRF is set with 1-bit or 8-bit memory manipulation instruction.
The value of this register is set to 0FH after reset and in the STOP mode.
In the HALT mode, it holds the value immediately before the HALT mode was set.
Figure 13-3. Format of PLL Reference Mode Register (PLLRF)
Symbol
7
6
5
PLLRF
0
0
0
PLLRF3 PLLRF2 PLLRF1 PLLRF0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
×
×
1
Note
When PLL disable is selected, the status of the VCOL, VCOH, EO0, and EO1 pins are as follows:
VCOH, VCOL pins: Status specified by bit 3 (VCOHDMD) and bit 2 (VCOLDMD) of the PLL mode
EO0, EO1 pins:
Remark Bits 4 to 7 are fixed to 0 by hardware.
×: Don't care
182
CHAPTER 13 PLL FREQUENCY SYNTHESIZER
of the PLL frequency synthesizer and sets the disabled status
r
4
<3>
<2>
<1>
<0>
0
PLLRF3 PLLRF2 PLLRF1 PLLRF0
Setting of reference frequency f
0
50 kHz
1
25 kHz
0
12.5 kHz
1
9 kHz
0
1 kHz
1
3 kHz
0
10 kHz
1
Setting prohibited
×
Note
PLL disable
select register (PLLMD).
High-impedance state
User's Manual U15104EJ2V0UD
Address
After reset
R/W
FFA1H
0FH
R/W
of PLL frequency synthesizer
r
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