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(3) PLL unlock F/F judge register (PLLUL)
This register detects whether the PLL frequency synthesizer is in the unlock status.
Because this register is an R&RESET register, it is reset to 0 after it has been read.
Reset input sets this register to 0×H
In the STOP and HALT modes, this register holds the value immediately before the STOP or HALT mode was
set.
Figure 13-4. Format of PLL Unlock F/F Judge Register (PLLUL)
Symbol
7
6
5
PLLUL
0
0
0
PLLUL0
0
Unlock F/F = 0: PLL lock status
1
Unlock F/F = 1: PLL unlock status
Notes 1. The value of bit 0 (PLLUL0) at reset differs depending on the type of reset that has been executed
(refer to the table below).
2. Bit 0 (PLLUL0) is R&Reset.
After reset Power-on clear
Watchdog timer
RESET input
STOP mode
HALT mode
Remark Bits 1 to 7 are fixed to 0 by hardware.
CHAPTER 13 PLL FREQUENCY SYNTHESIZER
Note 1
.
4
3
2
1
<0>
0
0
0
0
PLLUL0
Detection of status of unlock F/F
7
6
0
0
User's Manual U15104EJ2V0UD
Address
After reset
Note 1
FFA2H
0×H
R
5
4
3
2
0
0
0
0
R/W
Note 2
1
0
0
Undefined
Retained
Retained
Retained
Retained
183
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