Configuration Of Buzzer Output Controllers; Registers Controlling Buzzer Output Controllers; Beep0 - NEC mPD178054 Series User Manual

9.2 Configuration of Buzzer Output Controllers

The buzzer output controllers consist of the following hardware.

(1) BEEP0

Item
Control register
(2) BUZ
Item
Control register

9.3 Registers Controlling Buzzer Output Controllers

9.3.1 BEEP0
BEEP0 is controlled by the following register.
• BEEP clock select register 0 (BEEPCL0)
(1) BEEP clock select register 0 (BEEPCL0)
This register selects the frequency of the buzzer output.
BEEPCL0 is set with a 1-bit or 8-bit memory manipulation instruction.
Reset input clears this register to 00H.
Figure 9-3. Format of BEEP Clock Select Register 0 (BEEPCL0)
Symbol 7 6 5
BEEP
0 0 0
CL0
BEEP BEEP BEEP
CL02 CL01 CL00
× ×
0
1 0 0
0 0 1
1 1 0
1 1 1
Caution The selected clock may not be correctly output during the period of 1 cycle immediately after
the output clock has been changed.
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CHAPTER 9 BUZZER OUTPUT CONTROLLLER
Table 9-1. Configuration of Buzzer Output Controllers
BEEP clock select register 0 (BEEPCL0)
Clock output select register (CKS)
4 3 2 1 0
BEEP BEEP BEEP
0 0
CL02 CL01 CL00
Selection of frequency of BEEP0 output
Disables buzzer output (port function)
1 kHz
3 kHz
4 kHz
1.5 kHz
User's Manual U15104EJ2V0UD
Configuration
Configuration
Address After reset R/W
FF41H 00H R/W