NEC mPD178054 Series User Manual page 48

(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When IE = 0, all the interrupts are disabled (DI) except the non-maskable interrupt.
When IE = 1, the interrupts are enabled (EI). At this time, the acknowledging of interrupts is controlled
by the in-service priority flag (ISP), the interrupt mask flag corresponding to each interrupt, and the
interrupt priority specification flag.
The IE is reset to 0 upon DI instruction execution or interrupt acknowledgement and is set to 1 upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases.
(c) Register bank select flags (RBS0 and RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction
execution is stored.
(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in
all other cases.
(e) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupts.
When ISP = 0, acknowledging the vectored interrupt requests to which a low priority is assigned by the
priority specification flag registers (PR0L, PR0H) (refer to 12.3 (3) Priority specification flag registers
(PR0L, PR0H) is disabled. Whether an interrupt request is actually accepted depends on the status of
the interrupt enable flag (IE).
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out
value upon rotate instruction execution and functions as a bit accumulator during bit manipulation
instruction execution.
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CHAPTER 3 CPU ARCHITECTURE
User's Manual U15104EJ2V0UD