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U4 Pin Number
33
34
35
36
37
38
39
40
Notes:
*
Signal is optionally connected to power source through resistor DNI.
**
12 V power needs external supply from pin 8 of J4.
Table 8.8. FX12 U5 Header Pin Connections
U5 Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02052-0.90
Net Name
GND
GND
PWR_3-3V*
CH2_DATA1_P
CH2_DATA1_N
PWR_5-0V*
SDA1
SCL1
Net Name
CH1_DCK_P
CH1_DCK_N
GND
CH1_DATA0_P
CH1_DATA0_N
GND
CH1_DATA2_P
CH1_DATA2_N
GND
FX_SN
FX_SCLK
PWR_12V**
SDA2
SCL2
GND
CH3_DATA0_P
CH3_DATA0_N
GND
CH3_DCK_P
CH3_DCK_N
PWR_12V**
RESETN
PWR_5-0V*
CH1_DATA1_P
CH1_DATA1_N
PWR_3-3V*
CH1_DATA3_P
CH1_DATA3_N
PWR_1-8V
FX_MOSI
FX_MISO
PWR_1-8V*
GND
GND
PWR_3-3V*
MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
MachXO5-25 Ball Location
—
—
—
U10
V10
—
R4
R5
MachXO5-25 Ball Location
Y11
W11
—
V11
U11
—
V12
U12
—
V3
V4
—
R6
R7
—
T11
R11
—
Y12
W12
—
V2
—
Y14
W14
—
Y13
W13
—
U5
U6
—
—
—
—
25
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