Appendix A. Machxo5-Nx Development Board Schematics; Figure A.1. Title Page - Lattice Semiconductor MachXO5-NX User Manual

MachXO5-NX Development Board
Evaluation Board User Guide

Appendix A. MachXO5-NX Development Board Schematics

5
D
01 - Title Page
02 - Block Diagram and Power Tree
03 - USB to Hard JTAG I/F
C
04 - USB to Soft JTAG I/F (BANK1)
05 - Versa Connector (BANK0/2)
06 - Arduino&Aardvark Headers (BANK3/4)
07 - High Speed Headers (BANK5/6)
08 - Raspberry Pi and LEDs (BANK7/8)
B
09 - HyperRAM and ADC (BANK9)
10 - POWER RAILS
11 - POWER REGULATORS
A
5
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
38
4
MachXO5-NX Development Board
4

Figure A.1. Title Page

© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
3
Rev - A
Title Title Title
Title Page Title Page Title Page
Size Size Size Project Project Project
A A A MachXO5-NX Development Board MachXO5-NX Development Board MachXO5-NX Development Board
Date: Date: Date: Thursday, January 13, 2022 Thursday, January 13, 2022 Thursday, January 13, 2022
3
2 1
Lattice Semiconductor Applications Lattice Semiconductor Applications Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com Email: techsupport@Latticesemi.com Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE Phone (503) 268-8001 -or- (800) LATTICE Phone (503) 268-8001 -or- (800) LATTICE
Schematic Rev Schematic Rev Schematic Rev
Board Rev Board Rev Board Rev
Sheet Sheet Sheet 1 1 1 o f o f o f 11 11 11
2 1
D
C
B
A
1.0 1.0 1.0
A A A
FPGA-EB-02052-0.90