Table of Contents
Advertisement
MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
Table 4.2. Soft UART Connections
FTDI Signal
UBDBUS0
UBDBUS1
UBDBUS2
UBDBUS3
UBDBUS4
UBDBUS5
UBDBUS6
UBDBUS7
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16
UART Net Name
RS232_RX_TTL
RS232_TX_TTL
RTSn
CTSn
DTRn
DSRn
DCDn
RI
MachXO5-25 Ball Location for Port A
B11
B12
B13
B14
B15
B16
B17
C11
FPGA-EB-02052-0.90
Advertisement
Table of Contents
