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Table 9.4. Seven-Segment Display Connections - Lattice Semiconductor MachXO5-NX User Manual
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Table 9.4. Seven-segment Display Connections
Net Name
SEG_A
SEG_B
SEG_C
SEG_D
SEG_E
SEG_F
SEG_G
SEG_DP
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02052-0.90
D20 Pin Number
7
6
4
2
1
9
10
5
MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
MachXO5-25 Ball Location
F14
G11
E15
F11
A15
A16
A17
A18
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