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MachXO5-NX Development Board
Evaluation Board User Guide
5
HyperRAM and ADC
VRAM
U6
D
R152
A2
RFU1
A5
RFU2
4.7k
HR0_CS
A3
CS#
HR_RST
A4
RESET#
HR0_CKN
B1
CK#
HR0_CK
B2
CK
B3
VSS
C1
VSSQ_1
E5
VSSQ_2
CY-HyperRAM-S27KS0641DPBHI020
C
VCCIO9
F2
VCCIO9
H4
VCCIO9
C59
C60
0.1uF
0.1uF
B
VCCIO9
C58
10uF
MachXO5-NX
A
5
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
46
4
VRAM
VRAM
B4
VCC
R154
A2
E4
A5
VCCQ_1
D1
VCCQ_2
4.7k
HR1_CS
B5
A3
RFU3
HR_RST
C2
A4
RFU4
C5
RFU5
HR0_RW
HR1_CKN
C3
B1
RWDS
HR1_CK
B2
HR0_DQ0
D3
DQ0
HR0_DQ1
D2
DQ1
HR0_DQ2
C4
B3
DQ2
HR0_DQ3
D4
C1
DQ3
HR0_DQ4
D5
E5
DQ4
HR0_DQ5
E3
DQ5
HR0_DQ6
E2
DQ6
HR0_DQ7
E1
DQ7
U3J
27M_OSC
27M_OSC_OUT
B1
0
R72
PL2A/ ULC_GPLL0T_IN
27M_EN
27M_OSC_EN
C1
0
DNI
R161
PL2B
HR0_RW
D1
PL3B/ ULC_GPLL0T_MFGOUT2
HR_RST
D2
PL3A/ ULC_GPLL0T_MFGOUT1
HR1_DQ0
E1
PL5A
HR1_DQ1
E2
PL4B
HR1_DQ2
E3
PL4A
HR1_DQ3
F1
PL5B
HR1_DQ4
G1
PL8B
HR1_DQ5
G2
PL8A
HR1_DQ6
G3
PL7B
HR1_DQ7
G4
PL7A
HR1_RW
G5
PL6B
HR1_CS
G6
PL6A
HR0_DQ0
H1
PL11B
HR0_DQ1
H2
PL11A
DPHY0_SDA
H5
0
DNI
R228
PL10B
DPHY0_SCL
H6
0
DNI
R229
PL10A
DPHY0_RST
H7
PL9A
HR0_CKN
J1
PL15B
HR0_CK
J2
PL15A/ PCLKT9_0
HR0_CS
J3
PL14B
HR0_DQ2
J4
PL14A
HR0_DQ3
J5
PL13B
HR0_DQ4
J6
PL13A
HR0_DQ5
J7
PL9B
HR0_DQ6
J8
PL12A
HR1_CKN
K4
PL17B
HR1_CK
K5
PL17A/ PCLKT9_2
DPHY0_FSYNC
K6
DPHY0_FSYNC
PL16B
DPHY0_CLK
K7
DPHY0_CLK
PL16A/ PCLKT9_1
HR0_DQ7
K8
PL12B
DPHY0_SDA
DPHY0_SDA
DPHY0_SCL
DPHY0_SCL
4
Figure A.9. HyperRam and ADC (BANK9)
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
3
VRAM
U9
B4
VCC
E4
RFU1
VCCQ_1
D1
RFU2
VCCQ_2
B5
RFU3
C2
CS#
RFU4
C5
RESET#
RFU5
HR1_RW
C3
RWDS
CK#
HR1_DQ0
D3
CK
DQ0
HR1_DQ1
D2
DQ1
HR1_DQ2
C4
DQ2
HR1_DQ3
D4
VSS
DQ3
HR1_DQ4
D5
VSSQ_1
DQ4
HR1_DQ5
E3
VCCIO4
VSSQ_2
DQ5
HR1_DQ6
E2
DQ6
HR1_DQ7
E1
DQ7
CY-HyperRAM-S27KS0641DPBHI020
POT1
3314G-1-103E
VRAM
VRAM
FB7
MPZ1005S121CT000
R151
4.7k
HR_RST
R28
100K
X4
4
VDD
STDBY#
C34
100nF
2
GND
27MHZ
SDA0 [3,5,6,8]
SCL0 [3,5,6,8]
J28
DPHY0_RST
[7]
1
7
MDIR0
MDIR1
[8]
MDIR0
MEN0
2
8
MEN1
[8]
MEN0
ADCP0
3
9
ADCP1
ADCN0
4
10
ADCN1
5
11
[7]
[7]
6
12
PMOD 2x6
DNI
[7]
[7]
Target to support Type 5A for expended Dual H-Bridge
according PMOD spec v1.3.1
3
2
VCC_ADC
U3K
W16
VCCADC18
W15
FB8
ADC_REFP0
Y15
FB9
ADC_REFP1
W17
Y16
ADCP0
VSSADC
ADC_DP0
C62
C61
Y18
ADCP1
ADC_DP1
Y17
ADCN0
ADC_DN0
100nF
10uF
Y19
ADCN1
ADC_DN1
R80
R160
MachXO5-NX
1K
0
R168
VCC_CORE
0
1
1K
R82
POT1_WIPER
ADCP1
2
JP18
3
U3L
NC_PT01
NC_PT11
NC_PT02
NC_PT05
NC_PT12
NC_PT03
OSCILLATOR
NC_PT06
NC_PT13
NC_PT04
NC_PT14
NC_PT07
NC_PT08
27M_OSC_EN
1
NC_PT09
NC_PT10
NC_PR43
27M_OSC_OUT
3
OUT
NC_PR42
NC_PR41
NC_PL71
NC_PL72
NC_PR46
NC_PR45
NC_PR44
NC_PL73
NC_PL74
NC_PL75
NC_PL76
NC_PL77
MDIR1
[8]
MachXO5-NX
MEN1
[8]
VCCIO7
C126
100nF
Lattice Semiconductor Applications
Lattice Semiconductor Applications
Lattice Semiconductor Applications
Email:
Email:
Email:
techsupport@Latticesemi.com
techsupport@Latticesemi.com
techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Phone (503) 268-8001 -or- (800) LATTICE
Phone (503) 268-8001 -or- (800) LATTICE
Title
Title
Title
HyperRAM and ADC(BANK9)
HyperRAM and ADC(BANK9)
HyperRAM and ADC(BANK9)
Size
Size
Size
Project
Project
Project
B
B
B
MachXO5-NX Development Board
MachXO5-NX Development Board
MachXO5-NX Development Board
Date:
Date:
Date:
Thursday, January 13, 2022
Thursday, January 13, 2022
Thursday, January 13, 2022
2
1
+1.2V +1.8V
MPZ1005S121CT000
MPZ1005S121CT000
D
R169
+1.0V
0
0.01 ohm
R112
2
1
VCORE
C
A10
A19
B10
B18
B19
C10
C18
C19
D10
D18
E10
F10
G10
H10
V16
V17
V18
W5
W6
W18
W19
W20
B
Y2
Y3
Y4
Y5
Y6
A
1.0
1.0
1.0
Schematic Rev
Schematic Rev
Schematic Rev
Board Rev
Board Rev
Board Rev
A
A
A
Sheet
Sheet
Sheet
9
9
9
o f
o f
o f
11
11
11
1
FPGA-EB-02052-0.90
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