Table of Contents
Advertisement
MachXO5-NX Development Board
Evaluation Board User Guide
5
CrossLink Headers
D
U4
CH0_DCK_P
1
CH0_DCK_N
CH0_DCK_P
2
CH0_DCK_N
3
GND
CH0_DATA0_P
4
CH0_DATA0_N
CH0_DATA0_P
5
CH0_DATA0_N
6
GND
CH0_DATA2_P
7
CH0_DATA2_N
CH0_DATA2_P
8
CH0_DATA2_N
9
GND
FX_SN
10
FX_SCLK
SN
11
SCLK
+12V
12
PWR_12V
SDA2
13
SDA1
SCL2
14
SCL1
15
GND
CH2_DATA0_P
16
CH2_DATA0_N
CH2_DATA0_P
17
CH2_DATA0_N
18
CH2_DCK_P
GND
19
CH2_DCK_N
CH2_DCK_P
20
CH2_DCK_N
43
Shield3
44
Shield4
41
Shield1
Hirose - FX12 - 40 Pos
C
DNI
VCCIO5
PB38A/ VREF5_1/ADC_CP4/BDQ42
PB40A/ COMP1IP/PCLKT5_0/BDQ42
T12
VCCIO5
PB40B/ COMP1IN/PCLKC5_0/BDQ42
V14
VCCIO5
PB42A/ PCLKT5_1/ADC_CP8/BDQS42
PB42B/ PCLKC5_1/ADC_CN8/BDQSN42
C40
C41
PB46A/ PCLKT5_2/ADC_CP13/BDQ42
PB46B/ PCLKC5_2/ADC_CN13/BDQ42
0.1uF
0.1uF
VCCIO5
B
C39
10uF
PB58A/ PCLKT5_3/LRC_GPLL0T_MFGOUT1/BDQ54
PB58B/ PCLKC5_3/LRC_GPLL0T_MFGOUT2/BDQ54
PB60A/ LRC_GPLL0T_IN/ATB_FORCE/BDQ54
PB60B/ LRC_GPLL0C_IN/VREF5_2/ATB_SENSE/BDQ54
MachXO5-NX
+3.3V
+3.3V
R165
R166
1K
1K
A
D13
D14
Red
Red
SGMII_LED0
SGMII_LED1
Q2
Q3
MMBT3904
MMBT3904
5
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
44
4
+12V
+5.0V
+3.3V +1.8V
U5
CH1_DCK_P
21
1
PWR_12-0V
FX_RESETN
CH1_DCK_N
CH1_DCK_P
22
2
RESETN
CH1_DCK_N
23
3
PWR_5-0V
GND
CH0_DATA1_P
CH1_DATA0_P
24
4
CH0_DATA1_P
CH0_DATA1_N
CH1_DATA0_N
CH1_DATA0_P
25
5
CH0_DATA1_N
CH1_DATA0_N
26
6
PWR_3-3V
GND
CH0_DATA3_P
CH1_DATA2_P
27
7
CH0_DATA3_P
CH0_DATA3_N
CH1_DATA2_N
CH1_DATA2_P
28
8
CH0_DATA3_N
CH1_DATA2_N
29
9
PWR_1-8V
GND
FX_MOSI
FX_SN
30
10
MOSI
FX_MISO
FX_SCLK
SN
31
11
MISO
SCLK
+12V
32
12
PWR_1-8V
PWR_12_0V
33
SDA2
13
GND
SDA1
34
SCL2
14
GND
SCL1
35
15
PWR_3-3V
GND
CH2_DATA1_P
CH3_DATA0_P
36
16
CH2_DATA1_P
CH2_DATA1_N
CH3_DATA0_N
CH3_DATA0_P
37
17
CH2_DATA1_N
CH3_DATA0_N
38
18
PWR_5-0V
CH3_DCK_P
GND
39
SDA1
19
SDA
CH3_DCK_N
CH3_DCK_P
40
SCL1
20
SCL
CH3_DCK_N
45
43
Shield5
Shield3
46
44
Shield6
Shield4
42
41
Shield2
Shield1
+12V
+5.0V
+3.3V
+1.8V
Hirose - FX12 - 40 Pos
C24
C25
C26
C27
DNI
100nF
100nF
100nF
100nF
Note : Speed of the bus, < 2.5ps skew for pairs and
across the bus, traces should be 100 Ohms
Trace match LVDSI* pins between P and N channels as
well as individual pairs.
U3F
SDA1
[8]
SDA1
SCL1
[8]
SCL1
SDA2
[8]
SDA2
CH1_DATA0_P
V11
SCL2
[8]
SCL2
CH1_DATA0_N
U11
PB38B/ ADC_CN4/BDQ42
CH3_DATA0_P
T11
CH3_DATA0_N
R11
CH1_DCK_P
Y11
CH1_DCK_N
W11
VCCIO6
U3G
CH1_DATA2_P
V12
PB44A/ COMP2IP/BDQ42
CH1_DATA2_N
U12
PB44B/ COMP2IN/BDQ42
CH3_DCK_P
Y12
T9
VCCIO6
CH3_DCK_N
W12
V8
DPHY0_DP3
VCCIO6
N13
PB48A/ ADC_CP14/BDQ42
DPHY0_DN3
N12
PB48B/ ADC_CN14/BDQ42
C43
C44
PB6A/ PCLKT6_0/CDR_RXP0/ADC_CP0/COMP1P/BDQS6
0.1uF
0.1uF
PB6B/ PCLKC6_0/CDR_RXN0/ADC_CN0/COMP1N/BDQSN6
PB8A/ PCLKT6_1/ADC_CP1/COMP2P/BDQ6
PB8B/ PCLKC6_1/ADC_CN1/COMP2N/BDQ6
PB10A/ CDR_RXP1/ADC_CP3/BDQ6
PB10B/ CDR_RXN1/ADC_CN3/BDQ6
PB12A/ PCLKT6_2/ADC_CP2/COMP3P/BDQ6
PB12B/ PCLKC6_2/ADC_CN2/COMP3N/BDQ6
PB14A/ CDR0_TESTP/ADC_CP5/BDQ18
PB14B/ CDR0_TESTN/ADC_CN5/BDQ18
VCCIO6
PB16A/ CDR1_TESTP/ADC_CP7/BDQ18
PB16B/ CDR1_TESTN/ADC_CN7/BDQ18
C42
10uF
PB34A/ PCLKT6_3/ADC_CP10/BDQ18
DPHY0_DP0
U13
PB50A/ COMP3IP/BDQ54
DPHY0_DN0
PB34B/ PCLKC6_3/ADC_CN10/BDQ18
T13
PB50B/ COMP3IN/BDQ54
DPHY0_DP1
P13
PB52A/ ADC_CP11/BDQ54
DPHY0_DN1
R13
PB52B/ ADC_CN11/BDQ54
CH1_DATA3_P
Y13
PB54A/ ADC_CP12/BDQS54
CH1_DATA3_N
W13
PB54B/ ADC_CN12/BDQSN54
DPHY0_DP2
V13
PB56A/ ADC_CP15/BDQ54
DPHY0_DN2
U14
PB56B/ ADC_CN15/BDQ54
DPHY0_CKP
T14
DPHY0_CKN
R14
MachXO5-NX
CH1_DATA1_P
Y14
CH1_DATA1_N
W14
DPHY0_CKN
VRAM
DPHY0_CKP
DPHY0_DN3
DPHY0_DP3
R234
R233
DPHY0_DN1
DPHY0_DP1
4.7k
4.7k
DPHY0_SDA
[9]
DPHY0_SDA
DPHY0_SCL
DPHY0_DN0
[9]
DPHY0_SCL
DPHY0_CLK
DPHY0_DP0
[9]
DPHY0_CLK
DPHY0_FSYNC
+3.3V
[9]
DPHY0_FSYNC
DPHY0_RST
DPHY0_DN2
[9]
DPHY0_RST
DPHY0_DP2
R167
1K
DPHY0_CLK
DPHY0_FSYNC
DPHY0_SDA
D15
DPHY0_SCL
Red
VRAM
CVDD
DPHY0_RST
FB6
MPZ1005S121CT000
SGMII_LED2
+2.8V
Q4
MMBT3904
FB10
MPZ1005S121CT000
4
Figure A.7. High Speed Header (BANK5/6)
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
3
LVDS RX TERMINATION RESISTORS
R49
+12V
+5.0V +3.3V +1.8V
100
21
DNI
PWR_12V
FX_RESETN
22
RESETN
23
PWR_5-0V
CH1_DATA1_P
24
R53
CH1_DATA1_P
CH1_DATA1_N
25
100
CH1_DATA1_N
26
PWR_3-3V
CH1_DATA3_P
27
DNI
CH1_DATA3_P
CH1_DATA3_N
28
CH1_DATA3_N
29
PWR_1-8V
FX_MOSI
30
R57
MOSI
FX_MISO
31
100
MISO
32
PWR_1-8V
33
DNI
GND
34
GND
35
PWR_3-3V
CH3_DATA1_P
36
R61
CH3_DATA1_P
CH3_DATA1_N
37
100
CH3_DATA1_N
38
PWR_5-0V
39
SDA1
DNI
SDA
40
SCL1
SCL
45
Note :
Shield5
1) Match length within pair as well as other pairs with +/- 5% tolerence
46
Shield6
2)Differential impedance should be 100 Ohms and 50 Ohms as a single ended signals
3)All the power rails should be capable of carrying 1A current
+12V
+5.0V
+3.3V
+1.8V
42
Shield2
C20
C21
C22
C23
100nF
100nF
100nF
100nF
SGMII_PHY_COP
SGMII_FPGA_CLKP
C146
100nF
SGMII_PHY_CON
SGMII_FPGA_CLKN
C147
100nF
FX_MOSI
[8]
FX_MOSI
FX_MISO
SGMII_PHY_SOP
SGMII_FPGA_RXP
C148
100nF
[8]
FX_MISO
FX_SN
[8]
FX_SN
FX_SCLK
SGMII_PHY_SON
SGMII_FPGA_RXN
C149
100nF
[8]
FX_SCLK
FX_RESETN
[8]
FX_RESETN
SGMII_PHY_SIP
SGMII_FPGA_TXP
C150
100nF
SGMII_PHY_SIN
SGMII_FPGA_TXN
C151
100nF
R203
100
SGMII_FPGA_TXP
N8
PB2A/ VREF6_1/BDQ6
SGMII_FPGA_TXN
SGMII_PHY_SIP
P8
PB2B/ BDQ6
CH0_DATA0_P
SGMII_PHY_SIN
T8
PB4A/ BDQ6
CH0_DATA0_N
U8
PB4B/ BDQ6
CH0_DCK_P
W7
R205
100
CH0_DCK_N
Y7
CH2_DCK_P
W8
CH2_DCK_N
Y8
SGMII_FPGA_RXP
SGMII_PHY_COP
N9
SGMII_FPGA_RXN
SGMII_PHY_CON
P9
SGMII_FPGA_CLKP
U9
SGMII_FPGA_CLKN
SGMII_PHY_SOP
V9
SGMII_VDDIO
SGMII_PHY_SON
CH2_DATA0_P
N10
R66
2.49K
R68
DNI
0
CH2_DATA0_N
P10
CH0_DATA2_P
R10
CH0_DATA2_N
T10
CH0_DATA1_P
W9
PB18A/ ADC_CP6/BDQS18
CH0_DATA1_N
Y9
R36
100
PB18B/ ADC_CN6/BDQSN18
CH2_DATA1_P
SGMII_VDDIO
U10
PB32A/ ADC_CP9/BDQ18
CH2_DATA1_N
V10
PB32B/ ADC_CN9/BDQ18
CH0_DATA3_P
W10
CH0_DATA3_N
Y10
CH3_DATA1_P
N11
PB36A/ BDQ18
CH3_DATA1_N
P11
PB36B/ VREF6_2/BDQ18
R129
10K
SGMII_RST_N
SGMII_INT
R76
2.2K
SGMII_VDDIO
2
JP3
1
PHY_PD
J27
SGMII_LED2
SGMII_LED1
1
C178
C180
C179
C181
NC1
SGMII_LED0
2
CLK_N
3
10uF
10uF
1uF
1uF
CLK_P
4
R124
10K
R65
2.49K
DGND
5
DATA3_N
6
DATA3_P
7
DGND
8
C182
C183
C184
C185
DATA1_N
9
DATA1_P
10
0.1uF
0.1uF
0.1uF
1uF
DGND
11
DATA0_N
12
VCCA_1V_PHY
DATA0_P
13
DGND
14
DATA2_N
15
DATA2_P
16
C156
C157
DGND
17
J14
AF_GND
SGMII_MD0_P
18
1
10uF
10uF
AF_VDD2V8
SGMII_MD0_N
1
19
2
NC2
SGMII_MD1_P
2
20
3
MCLK
SGMII_MD1_N
3
21
4
NC3
4
SGMII_MD2_P
22
5
SDA
SGMII_MD2_N
5
23
6
SCL
+2.5V
SGMII_MD3_P
6
24
7
RESET
7
SGMII_MD3_N
25
8
VDD1.05V
8
26
R67
DNI
0
9
DVDD1V8
9
27
10
DGND
10
28
AGND
29
C28
AVDD2V8
7498111001-RJ45
30
AGND
18pF
245804030000829+
3
2
1
NOTE : PLACE ALL THE TERMINATION
RESISTORS ON TOP SIDE AND CLOSE
TO THE U3
CH0_DCK_P
CH0_DATA3_P
CH1_DATA2_P
CH2_DATA1_P
R50
R51
R52
100
100
100
CH0_DCK_N
CH0_DATA3_N
CH1_DATA2_N
CH2_DATA1_N
DNI
DNI
DNI
CH0_DATA0_P
CH1_DCK_P
CH1_DATA3_P
CH3_DCK_P
R54
R55
R56
100
100
100
CH0_DATA0_N
CH1_DCK_N
CH1_DATA3_N
CH3_DCK_N
DNI
DNI
DNI
CH0_DATA1_P
CH1_DATA0_P
CH2_DCK_P
CH3_DATA0_P
R58
R59
R60
100
100
100
CH0_DATA1_N
CH1_DATA0_N
CH2_DCK_N
CH3_DATA0_N
DNI
DNI
DNI
CH0_DATA2_P
CH1_DATA1_P
CH2_DATA0_P
CH3_DATA1_P
R62
R63
R64
100
100
100
CH0_DATA2_N
CH1_DATA1_N
CH2_DATA0_N
CH3_DATA1_N
DNI
DNI
DNI
SGMII_XO
SGMII_XI
1M Ohm
SGMII_CLK_OUT
R158
[8]
SGMII_CLK_OUT
SGMII_RST_N
[8]
SGMII_RST_N
X3
2
SGMII_INT
[8]
SGMII_INT
ABM3-25
SGMII_MDIO_CLK
25 MHz
[8]
SGMII_MDIO_CLK
C18
SGMII_MDIO_DATA
[8]
SGMII_MDIO_DATA
18pF
+2.5V
+2.5V
U7
C166
C169
C167
C168
25
3
TX_D3
VDDA2P5
26
9
10uF
10uF
1uF
1uF
TX_D2
VDDA2P5
27
TX_D1/SGMII_SIP
SGMII_MD0_P
28
1
TX_D0/SGMII_SIN
TD_P_A
SGMII_MD0_N
2
TD_M_A
SGMII_MD1_P
29
4
C171
C170
GTX_CLK
TD_P_B
SGMII_MD1_N
5
TD_M_B
SGMII_MD2_P
32
7
0.1uF
0.1uF
RX_CLK
TD_P_C
SGMII_MD2_N
8
TD_M_C
SGMII_MD3_P
33
10
RX_D0/SGMII_COP
TD_P_D
SGMII_MD3_N
34
11
RX_D1/SGMII_CON
TD_M_D
35
RX_D2/SGMII_SOP
SGMII_PHY_D1V8
+1.8V
36
12
R32
11K
1%
RX_D3/SGMII_SON
RBIAS
48
VDDA1P8
37
13
FB1
TX_CTRL
VDDA1P8
38
MPZ1005S121CT000
RX_CTRL
SGMII_XO
14
XO
SGMII_XI
39
15
GPIO_0
XI
40
SGMII_VDDIO
GPIO_1
SGMII_MDIO_CLK
16
R38
DNI
2.2K
MDC
SGMII_MDIO_DATA
41
17
R77
2.2K
VDDIO
MDIO
19
VDDIO
30
VDDIO
SGMII_CLK_OUT
18
R75
22
CLK_OUT
43
RESET
20
R89
100
JTAG_CLK
44
21
R219
2.2K
INT/PWDN
JTAG_TDO
22
R220
2.2K
JTAG_TMS
23
R221
2.2K
JTAG_TDI
45
42
LED_2
VDD1P0
VCCA_1V_PHY
+1.0V
46
24
LED_1
VDD1P0
47
6
LED_0
VDD1P0
31
VDD1P0
FB12
SGMII_PHY_D1V8
MPZ1005S121CT000
DP83867ERGZT
C172
C174
C173
C175
C176
10uF
10uF
1uF
1uF
0.1uF
C158
C159
C160
C161
1uF
1uF
1uF
1uF
C162
C163
C164
C165
0.1uF
0.1uF
0.1uF
0.1uF
Lattice Semiconductor Applications
Lattice Semiconductor Applications
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Email: techsupport@Latticesemi.com
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Phone (503) 268-8001 -or- (800) LATTICE
Phone (503) 268-8001 -or- (800) LATTICE
Title
Title
Title
High Speed Heads(BANK5/6)
High Speed Heads(BANK5/6)
High Speed Heads(BANK5/6)
Size
Size
Size
Project
Project
Project
C
C
C
MachXO5-NX Development Board
MachXO5-NX Development Board
MachXO5-NX Development Board
Date:
Date:
Date:
Thursday, January 13, 2022
Thursday, January 13, 2022
Thursday, January 13, 2022
Sheet
Sheet
Sheet
2
1
D
C
1
C19
18pF
B
C177
0.1uF
A
1.0
1.0
1.0
Schematic Rev
Schematic Rev
Schematic Rev
Board Rev
Board Rev
Board Rev
A
A
A
7
7
7
o f
o f
o f
11
11
11
FPGA-EB-02052-0.90
Advertisement
Table of Contents
