Lattice Semiconductor MachXO5-NX User Manual page 4

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MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
Figures
Figure 1.1. Top View of MachXO5-NX Development Board ................................................................................................. 7
Figure 1.2. Bottom View of MachXO5-NX Development Board ........................................................................................... 8
Figure 2.1. Board Power Supply.......................................................................................................................................... 10
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C Programming Architecture ................................................................................................................ 12
Figure 3.2. Radiant Programmer Detect Dual Ports ........................................................................................................... 12
Figure 3.3. Level Shift for JTAG Download Interface .......................................................................................................... 13
Figure 3.4. JTAG Test Header .............................................................................................................................................. 13
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C Programming Mode .................................................................................................................................... 14
Figure 4.1. JTAG/UART User Interfacing ............................................................................................................................. 15
Figure 5.1. Onboard Clock Resources ................................................................................................................................. 17
Figure 8.1. MIPI Camera Sensor Interface .......................................................................................................................... 28
Figure 8.2. MIPI Camera Sensor Power Supply Header ...................................................................................................... 29
Figure 8.3. Circuit Design for ADC0 ..................................................................................................................................... 30
Figure 8.4. Circuit Design for ADC1 ..................................................................................................................................... 31
Figure 8.5. Trimmer Wiper Description .............................................................................................................................. 31
Figure 9.1. Four-Position DIP Switch Circuits ...................................................................................................................... 33
Figure 9.2. Four-position DIP Switch .................................................................................................................................. 33
Figure 9.3. Seven-Segment Display and its Symbol ............................................................................................................ 34
Figure A.1. Title Page .......................................................................................................................................................... 38
Figure A.2. Block Diagram and Power Tree ........................................................................................................................ 39
Figure A.3. USB to Hard JTAG I/F ........................................................................................................................................ 40
Figure A.4. USB to Soft JTAG I/F (BANK1) ........................................................................................................................... 41
Figure A.5. Versa Connector (BANK0/2) ............................................................................................................................. 42
Figure A.6. Arduino&Aardvark Header (BANK3/4) ............................................................................................................. 43
Figure A.7. High Speed Header (BANK5/6) ......................................................................................................................... 44
Figure A.8. Raspberry Pi and LEDs (BANK7/8) .................................................................................................................... 45
Figure A.9. HyperRam and ADC (BANK9) ............................................................................................................................ 46
Figure A.10. Power Rails ..................................................................................................................................................... 47
Figure A.11. Power Regulators ........................................................................................................................................... 48
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-EB-02052-0.90

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