MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
Figures
Figure 2.1. Board Power Supply.......................................................................................................................................... 10
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C Programming Architecture ................................................................................................................ 12
Figure 3.4. JTAG Test Header .............................................................................................................................................. 13
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C Programming Mode .................................................................................................................................... 14
Figure A.1. Title Page .......................................................................................................................................................... 38
Figure A.3. USB to Hard JTAG I/F ........................................................................................................................................ 40
Figure A.10. Power Rails ..................................................................................................................................................... 47
Figure A.11. Power Regulators ........................................................................................................................................... 48
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FPGA-EB-02052-0.90