Appendix C. User Defined Preference File Listing - Lattice Semiconductor MachXO5-NX User Manual

MachXO5-NX Development Board
Preliminary Evaluation Board User Guide

Appendix C. User Defined Preference File Listing

// These names follow the MachXO5™-NX Development Board schematic but,
// they may be defined by the user.
// preference file and edited to match a different naming convention if
// needed or used to fill in the Spreadsheet view.
// MachXO5-25 LED Connections
// Note: The following order matches the LED locations on the board
// from top D1 to bottom D8
ldc_set_location -site {R3} [get_ports {LED[0]}]
ldc_set_location -site {R2} [get_ports {LED[1]}]
ldc_set_location -site {R1} [get_ports {LED[2]}]
ldc_set_location -site {P7} [get_ports {LED[3]}]
ldc_set_location -site {H12} [get_ports {LED[4]}]
ldc_set_location -site {H11} [get_ports {LED[5]}]
ldc_set_location -site {G13} [get_ports {LED[6]}]
ldc_set_location -site {G12} [get_ports {LED[7]}]
//DIP Switch Connections
ldc_set_location -site {T1} [get_ports {DIPSW[0]}]
ldc_set_location -site {T2} [get_ports {DIPSW[1]}]
ldc_set_location -site {T3} [get_ports {DIPSW[2]}]
ldc_set_location -site {T4} [get_ports {DIPSW[3]}]
//Push Button Connections
ldc_set_location -site {E19} [get_ports PB1]
ldc_set_location -site {F20} [get_ports PB2]
ldc_set_location -site {B7}
ldc_set_location -site {G20} [get_ports PB4]
//Clock inputs
ldc_set_location -site {E14} [get_ports CLK_12MHz]
ldc_set_location -site {T7}
ldc_set_location -site {B1}
ldc_set_location -site {V1}
ldc_set_location -site {D19} [get_ports CLK_EXT]
//SEG LED Connections
ldc_set_location -site {A18} [get_ports SEG_LED_DP]
ldc_set_location -site {A17} [get_ports SEG_LED_G]
ldc_set_location -site {A16} [get_ports SEG_LED_F]
ldc_set_location -site {A15} [get_ports SEG_LED_E]
ldc_set_location -site {F11} [get_ports SEG_LED_D]
ldc_set_location -site {E15} [get_ports SEG_LED_C]
ldc_set_location -site {G11} [get_ports SEG_LED_B]
ldc_set_location -site {F14} [get_ports SEG_LED_A]
//HyperRAM
ldc_set_location -site {D2} [get_ports ram0_1_rst]
ldc_set_location -site {J2} [get_ports ram0_ck_p]
ldc_set_location -site {J1} [get_ports ram0_ck_n]
ldc_set_location -site {J3} [get_ports ram0_cs]
ldc_set_location -site {H1} [get_ports ram0_dq0]
ldc_set_location -site {H2} [get_ports ram0_dq1]
ldc_set_location -site {J4} [get_ports ram0_dq2]
ldc_set_location -site {J5} [get_ports ram0_dq3]
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Thus, they can be copied into the
[get_ports PB3]
[get_ports CLK_25MHz]
[get_ports CLK_27MHz]
[get_ports CLK_125MHz]
FPGA-EB-02052-0.90