Features; Figure 1.2. Bottom View Of Machxo5-Nx Development Board - Lattice Semiconductor MachXO5-NX User Manual

MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
User USB
Header (J19)
12V DC Power
Jack (J17)

1.2. Features


On board MachXO5-25 Device

Optional SGMII, Gbe PHY RJ45 connector (Check Appendix D for the board revision information)

HyperRAM upto 166MHz, x16 bits

Versa Headers bridge with Lattice ASC Demo Board to support L-ASC10

General Purpose Input/Output (GPIO) interface with PMOD, Arduino and Raspberry Pi boards

USB-B connection for device programming with JTAG and Inter-Integrated Circuit (I

Additional USB-B connection for user with Soft JTAG and UART utility

7-Segment Blue LED, 4-position DIP Switches, 4 push buttons, and 8 red LEDs for demo purposes

ADC interface with 10K POT

Two Hirose FX12-40 headers

Multiple reference clock sources

Optional Aardvark header

Lattice Radiant ® programming support
Note: DNI stands for "Do NOT Install" parts and DI stands for "Do Install" parts for assembly.
Caution: The MachXO5-NX Development Board contains ESD-sensitive components. ESD safe
practices should be followed while handling and using the development board.
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8
Config FTDI
User FTDI
Device (U1)
Device (U18)

Figure 1.2. Bottom View of MachXO5-NX Development Board

Config USB 125MHz
27MHz
Header (J11) Clock (X5)
Clock (X4)
2
C) utility
FPGA-EB-02052-0.90