Table of Contents
Advertisement
MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
1.3. MachXO5-25 Device
The MachXO5-NX Development Board features the MachXO5-25 in a 400-ball caBGA package. This device offers a
variety of features and programmability that enhances Secure Control PLD functionality with Multiple Boot capabilities.
Its cryptographic engine supports user-mode security features. Along with the cryptographic engine, numerous system
functions are included such as two PLLs and 432 kbits of embedded RAM plus hardened implementations of I
2
C and SPI.
Flexible, high performance I/O support numerous single-ended and differential standards including LVDS and MIPI. For
more information on the capabilities of MachXO5-25 device, see MachXO5-NX Family Data Sheet (FPGA-DS-02102).
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02052-0.90
9
Advertisement
Table of Contents
