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MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
9.2. General Purpose Push Buttons
The MachXO5-NX Development Board provides four push button switches, SW2, SW3, SW4 and SW5, for demos and
user applications. Pressing these buttons drives a logic level 0 to the corresponding I/O pins.
Table 9.2. Push Button Switch Signals
Push Button Ref Name
SW2
SW3
SW4
SW5
SW2 and SW3 are designed for general-purpose applications. SW4 and SW5 are designed with additional jumper JP4
and JP5. SW4 can be used as ASC global reset push button when JP4 is set to connect with EXPCON_IO20, which is
connect to MANDATORY_RESET signal when mated with Lattice ASC Bridge Board. Refer to
Evaluation Board User Guide (FPGA-EB-02025)
PROGRAMN push button when JP5 is set to trigger the configuration process without power cycle. For detailed
information on PROGRAMN, refer to MachXO5 Programming and Configuration User Guide (FPGA-TN-02271).
9.3. General Purpose LEDs
The MachXO5-NX Development Board provides eight red LEDs that are connected to I/O within Bank 5. The LEDs are
lighted when the output is driven LOW.
Table 9.3. LED Signals
Red LEDs Ref Name
D1
D2
D3
D4
D5
D6
D7
D8
9.4. Seven-Segment Display
The MachXO5-NX Development Board features a blue Seven-segment Display of D20, as shown in
by I/O within Bank 5. Each segment LED is lighted blue when the output is driven LOW.
between display LED segments and their associated driver pins.
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
34
Net Name
PB1
PB2
PB3
PB4
for detailed information with ASC application. SW5 can be used as
Table 9.3
lists the red LEDs and their associated pins.
Net Name
XLED0
XLED1
XLED2
XLED3
XLED4
XLED5
XLED6
XLED7
Figure 9.3. Seven-Segment Display and its Symbol
MachXO5-25 Ball Location
E19
F20
B7
G20
MachXO5-25 Ball Location
Table 9.4
Test Points
TP3
TP4
Pin 2 of JP4
Pin 2 of JP5
ASC Bridge Board
R3
R2
R1
P7
H12
H11
G13
G12
Figure
9.3, controlled
lists the connections
FPGA-EB-02052-0.90
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