Elnec MEMprog2 User Manual page 31

BeeProg2 / BeeProg+
Built-in protection circuits eliminate damage of programmer and/or programmed device due
environment or operator failure. All the inputs of the BeeProg2 / BeeProg+ programmer,
including the ZIF socket, ISP connector, connection to PC and power supply input, are
protected against ESD up to 15kV.
BeeProg2 / BeeProg+ programmer performs programming verification at the marginal
level of supply voltage, which, obviously, improves programming yield, and guarantees long
data retention.
Various socket converters are available to handle device in PLCC, SOIC, PSOP, SSOP,
TSOP, TSSOP, TQFP, QFN (MLF), SDIP, BGA and other packages.
BeeProg2 / BeeProg+ programmer is driven by an easy-to-use control program with pull-
down menu, hot keys and on-line help. Selecting of device is performed by its class, by
manufacturer or simply by typing a fragment of vendor name and/or part number.
Standard device-related commands (read, blank check, program, verify, erase) are boosted
by some test functions (insertion test, signature-byte check), and some special functions
(autoincrement, production mode - start immediately after insertion of chip into socket).
All known data formats are supported. Automatic file format detection and conversion during
load of file.
The rich-featured autoincrement function enables to assign individual serial numbers to
each programmed device - or simply increments a serial number, or the function enables to
read serial numbers or any programmed device identification signatures from a file.
The software also provides a lot of information about programmed device. As a special, the
drawings of all available packages, explanation of chip labeling (the meaning of prefixes
and suffixes at the chips) for each supported chip are provided.
The software provide full information for ISP implementation: Description of ISP connector
pins for currently selected chip, recommended target design around in-circuit programmed
chip and other necessary information.
The remote control feature allows being Pg4uw software flow controlled by other application
– either using .BAT file commands or using DLL file. DLL file, examples
(C/PAS/VBASIC/.NET) and manual are part of standard software delivery.
Jam files of JEDEC standard JESD-71 are interpreted by Jam Player. Jam files are
generated by design software which is provided by manufacturer of respective programmable
device. Chips are programmed in ZIF or through ISP connector (IEEE 1149.1 Joint Test
Action Group (JTAG) interface).
VME files are interpreted by VME Player. VME file is a compressed binary variation of SVF
file and contains high-level IEEE 1149.1 bus operations. VME files are generated by design
software which is provided by manufacturer of respective programmable device. Chips are
programmed in ZIF or through ISP connector (IEEE 1149.1 Joint Test Action Group (JTAG)
interface).
Multiple devices are possible to program and test via JTAG chain: JTAG chain (ISP-Jam) or
JTAG chain (ISP-VME).
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