Xilinx Zynq-7000 User Manual page 47

Relative address
Table A-2: Global Interrupt Enable Register
Bit Position
31:1
0
Interrupt Enable Register
The relative address of the Interrupt Enable register is 0x08.
register's structure.
Relative address
Table A-3: Interrupt Enable Register
Bit Position
31:1
0
Interrupt Status Register
The relative address of the Interrupt Status register is 0x0C.
register's structure.
Relative address
Table A-4: Interrupt Status Register
Bit Position
31:2
1
0
Number of Rows Register
The relative address of the Number of Rows register is 0x14.
register's structure.
Zynq-7000 AP SoC ZC702 Base TRD
UG925 (v6.0) February 21, 2014
0x04
Mode Default Value
- -
RW
0x0
0x08
Mode Default Value
- -
RW
0x0
0x0C
Mode Default Value
- -
RW
0x0
RW
0x0
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Description
Reserved.
Global interrupt enable.
Table A-3
Description
Reserved.
Frame processing done interrupt enable.
Table A-4
Description
Reserved.
IP ready interrupt status.
Frame processing done interrupt status.
Table A-5
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Sobel Filter Registers
describes this
describes this
describes this
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