Xilinx Zynq-7000 User Manual page 24

the maximum burst length is set to 16. In addition, the master interfaces have a read and
write issuance of 8 and a read and write FIFO depth of 512 to maximize throughput. The line
buffers inside the AXI VDMA for the read and write sides are set to 4K deep and the store
and forward feature of the AXI VDMA are enabled on both channels to improve system
performance and reduce the risk of system throttling.
For detailed information on the complete feature set and a functional description of AXI
VDMA IP, see the LogiCORE IP AXI Video Direct Memory Access Product Guide (PG020)
[Ref 5].
Video Timing Controller
Instance: system_top_i/Video_Capture/VTC_0
The VTC is a general purpose video timing generator and detector. The input side of this
core automatically detects horizontal and vertical synchronization pulses, polarity, blanking
timing, and active video pixels. This information can be used by application software to take
various decisions and for configuration of the video pipeline. In the current design,
application software measures resolution of external video and then decides whether to
switch to the external video source or not. The same feature can be expanded in the future
to configure the video pipeline based on input resolution.
The output side of the core generates the horizontal and vertical blanking and
synchronization pulses. The width and interval of these pulses are configured through the
AXI Lite interface. The AXI TPG block generates a video test pattern based on video timing
pulses generated by VTC. In this design, VTC is used to generate video timing signals to
match Full HD (1080p60) video format.
The video timing generator/detector block and AXI Lite interface of this core work on a
single clock domain (i.e., the video clock).
For detailed information on the complete feature set, a functional description, and licensing
information for Video Timing Controller IP, see the LogiCORE IP Video Timing Controller
Product Guide (PG016)
Test Pattern Generator
Instance: system_top_i/Video_Capture/TPG_0
The Test Pattern Generator contains an AXI register interface to access slave control
registers from a processor. This IP can generate patterns like color bars, horizontal and
vertical burst patterns, and zone plates. The generation of pattern is controlled through the
pattern control register. It also enables the overlay of a box on a selected pattern. The
motion control register controls the speed at which the box moves over a selected pattern.
In this design, a zone plate pattern is used with a moving box. The size of the zone plate is
controlled through zplate hdelta and zplate vdelta registers. The box size register controls
the size of the box, and the color of the box is selected by the box color register. The width
Zynq-7000 AP SoC ZC702 Base TRD
UG925 (v6.0) February 21, 2014
[Ref 6].
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Hardware Architecture
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