Xilinx Zynq-7000 User Manual page 27

This IP generates an interrupt after processing every frame, then the software initiates the
process for the next frame by writing to the control register.
Video In to AXI4-Stream
Instance: system_top_i/Video_Capture/VID_IN_AXI4S
This IP interfaces a video source to the AXI4-Stream interface. It also handles video data
clock boundary crossing between the video clock domain and AXI4-Stream clock domain.
For detailed information on the complete feature set and a functional description of Video
in to AXI4-Stream IP, see the LogiCORE IP Video In to AXI4-Stream v1.0 (PG043)
Video Color Space Formats
Table 2-7 shows the video color space formats available in the video pipeline.
Table 2-7: Video Color Space formats
Video IP
HDMI_IN (ADV7611)
VID_IN_AXI4S
TPG_0 (Test Pattern Generator)
CRESAMPLE_0
YUV2RGB_0
TPG_VDMA (S2MM)
FILTER_VDMA (S2MM & MM2S)
Sobel Filter
LogiCVC
HDMI_OUT (ADV7511)
Because both VDMAs operate on ARGB 32 bpp, the DDR memory always has the ARGB
32 bpp video format.
I2C Sub-system
I2C is a two-wire bus for attaching low-speed peripherals. It uses two bi-directional
open-drain lines, SDA (serial data) and SCL (serial clock), pulled up with resistors. In
standard mode, a 7-bit address space and a 100 kHz bus speed are used. In this reference
design, the two PS I2C controllers are used as bus masters to configure a number of I2C
slaves or clients. The bus hierarchy is shown in
Zynq-7000 AP SoC ZC702 Base TRD
UG925 (v6.0) February 21, 2014
Input Video Format
YCbCr 4:2:2
YCbCr 4:2:2
YCbCr 4:4:4
ARGB 32 bpp
ARGB 32 bpp
YCbCr 4:2:2
Figure 2-2.
www.xilinx.com
Hardware Architecture
[Ref 12].
Output Video Format
YCbCr 4:2:2
YCbCr 4:4:4
ARGB 32 bpp
ARGB 32 bpp
YCbCr 4:2:2
RGB
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