Xilinx Zynq-7000 User Manual page 21

Table 2-6: PL Clock Configuration (Cont'd)
Component
axi4_1
• INTERCONNECT_ACLK
axi4_lite
• INTERCONNECT_ACLK
Peripherals
proc_sys_reset_1
• Slowest_sync_clk
LOGICVC_0
• S_AXI_ACLK
• mclk
• vclk
FILTER_ENGINE
• SYS_CLK
• s_axi_CONTROL_BUS_ACLK
SOBEL_SWRST_FF
• Clk
FILTER_VDMA
• m_axi_mm2s_aclk
• m_axi_s2mm_aclk
• m_axis_mm2s_aclk
• s_axi_lite_aclk
• s_axis_s2mm_aclk
TPG_SWRST_FF
• Clk
TPG_VDMA
• m_axi_s2mm_aclk
• s_axi_lite_aclk
• s_axis_s2mm_aclk
PERF_MON_HP0_HP2
• SLOT_0_AXI_ACLK
• SLOT_1_AXI_ACLK
• S_AXI_ACLK
• CORE_ACLK
VTC_0
Zynq-7000 AP SoC ZC702 Base TRD
UG925 (v6.0) February 21, 2014
Frequency (MHz) Phase Buffered
150 0
75 0
75 0
75 0
150 0
148.5 0
150 0
150 0
75 0
150 0
150 0
150 0
75 0
150 0
75 0
150 0
75 0
150 0
150 0
150 0
75 0
150 0
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Hardware Architecture
Connection
Yes clk_150mhz
Yes clk_75mhz
Yes clk_75mhz
Yes clk_75mhz
Yes clk_150mhz
Yes VIDEO_CLK
Yes clk_150mhz
Yes clk_150mhz
Yes clk_75mhz
Yes clk_150mhz
Yes clk_150mhz
Yes clk_150mhz
Yes clk_75mhz
Yes clk_150mhz
Yes clk_75mhz
Yes clk_150mhz
Yes clk_75mhz
Yes clk_150mhz
Yes clk_150mhz
Yes clk_150mhz
Yes clk_75mhz
Yes clk_150mhz
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