Xilinx Zynq-7000 User Manual page 18

IPs provided by Xilinx are AXI4-compliant, and the soft AXI interconnect IP provides
protocol bridging as needed.
S_AXI_HP - The high performance slave AXI interfaces (S_AXI_HP) connect the PL to AFI
blocks in the PS. The PL has four AXI masters out of which two are connected to the
S_AXI_HP0 port and two are connected to the S_AXI_HP2 port. The HP port enables a high
throughput data path between AXI masters in the programmable logic and the processing
system's DDR3 memory. The main aim of the AXI FIFO interface (AFI) units is to smooth out
this variable latency, allowing the ability to stream data continuously from DDR to the PL
masters and from the PL masters to DDR. The PL-side interface of AFI runs on the clock
coming from the PL. In this design, a 150 MHz clock is connected from the PL side. The
DDR-side clock is running on 2/3 of the DDR_CLK (533 MHz). The high performance AXI
interface module provides several hooks to assist in bandwidth management of masters
connected to different PL ports. Controlling issuance capability available from the PL port is
one of the hooks exercised in this design to obtain a fair share of bandwidth between two
masters, SOBEL VDMA, and the display controller.
M_AXI_GP - This AXI master port interfaces with AXI slave IPs in PL through an AXI Lite
interconnect. The CPU manages initializing and controlling the video pipeline through this
port.
IOP - The IOP unit includes communication peripherals. GPIO, Ethernet, USB, I2C, and SD
controllers from the PS are used extensively in this design.
GPIO - The 64-bit general purpose input/outputs (GPIOs) are connected to the PL through
the extendable multiplexed I/O (EMIO) interface. Sixty-four bits are divided into two banks,
each of 32 bits. Because each GPIO bit can be dynamically configured as input or output,
GPIO bits are used in this design for a variety of functions.
purpose in design.
Table 2-4: GPIO Bits Functional Description
GPIO Bit
Net Name
Number
0 ps7_0_GPIO_O[0]
1 ps7_0_GPIO_O[1]
3 ps7_0_GPIO_O[3]
6 ps7_0_GPIO_O[6]
2, 4, 5, 7 N/A
Memory Interfaces
The memory interfaces unit includes the DDR memory controller and nonvolatile memory
(NVM) controllers. The DDR memory controller includes a 4-port arbiter. One AXI port is
dedicated for ARM CPU access and two ports are dedicated for high performance AXI
interface master devices in the programmable logic. The remaining port is shared by all
Zynq-7000 AP SoC ZC702 Base TRD
UG925 (v6.0) February 21, 2014
Resets video receiving block VID_IN_AXI4s
Resets Sobel filter block
Selects a line for the video multiplexer—either the external video
source or the internally generated test pattern
FMC-IMAGEON I2C multiplexer reset
N/A
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Hardware Architecture
Table 2-4 lists the GPIO bit and
Purpose
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