Xilinx Zynq-7000 User Manual page 54

Relative address
Table A-25: High Threshold Register
Bit Position
31:8
7:0
Low Threshold Register
The relative address of the Low Threshold register is 0xBC.
register's structure.
Relative address
Table A-26: Low Threshold Register
Bit Position
31:8
7:0
Invert Output Register
The relative address of the Invert Output register is 0xC4.
register's structure.
Relative address
Table A-27: Invert Output Register
Bit Position
31:1
0
Zynq-7000 AP SoC ZC702 Base TRD
UG925 (v6.0) February 21, 2014
0xB4
Mode Default Value
-
-
RW
0x0
0xBC
Mode Default Value
-
-
RW
0x0
0xC4
Mode Default Value
RW
0x0
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Description
Reserved.
High Threshold for Sobel filtering.
Table A-26
Description
Reserved.
Low Threshold for Sobel filtering.
Table A-27
Description
Reserved.
Inverts output of Sobel filter.
Sobel Filter Registers
describes this
describes this
54
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