Xilinx Zynq-7000 User Manual page 20

Table 2-5: System Clocks
Clock Signal
FPGA_CLK
clk_75mhz
clk_150mhz
VIDEO_CLK_P, VIDEO_CLK_N
fmc_imageon_in_0_clk_pin
Based on user clock configuration inputs, the clock generator determines the correct
configuration of the PLLs.
Table 2-6 shows clock requirements of master and slave peripherals connected in system
and their connection.
Table 2-6: PL Clock Configuration
Component
clock_generator_0
• CLKIN
• CLKOUT0
• CLKOUT1
VIDEO_MUX_0
• video_clk_1
• video_clk_2
• video_clk
Processor
ps7_0
• FCLK_CLK0
• M_AXI_GP0_ACLK
• S_AXI_HP0_ACLK
• S_AXI_HP2_ACLK
Buses
axi4_0
• INTERCONNECT_ACLK
Zynq-7000 AP SoC ZC702 Base TRD
UG925 (v6.0) February 21, 2014
Source
PS - FCLK_CLK0
Internal mixed-mode clock
manager (MMCM)
Internal MMCM
External differential video
clock coming from clock
synthesizer on board
External video clock coming
from Imageon FMC
Frequency (MHz) Phase Buffered
100
75
150
148.5 0
148.5 0
148.5 0
100 0
75 0
150 0
150 0
150 0
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Hardware Architecture
Frequency
100 MHz Input clock to clock
generator
75 MHz Clock for AXI Lite
interconnect, generated
by clock generator
150 MHz Clock for AXI MM
interconnect, generated
by clock generator
148.5 MHz Clock for display
controller and video
receiving blocks
148.5 MHz Clock for video receiving
modules
Connection
Yes FPGA_CLK
Yes clk_75mhz
Yes clk_150mhz
Yes VIDEO_CLK
Yes fmc_imageon_hdmi_in_0_clk_pin
Yes video_clk_int
Yes FPGA_CLK
Yes clk_75mhz
Yes clk_150mhz
Yes clk_150mhz
Yes clk_150mhz
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