Xilinx Zynq-7000 User Manual page 22

Table 2-6: PL Clock Configuration (Cont'd)
Component
• clk
• S_AXI_ACLK
TPG_0
• aclk
• s_axi_aclk
HDMI_IN
• clk
VID_IN_AXI4S
• vid_in_clk
• aclk
CRESAMPLE_0
• aclk
• s_axi_aclk
YUV2RGB_0
• aclk
• s_axi_aclk
Processor System Reset Module
Instance: system_top_i/proc_sys_reset_1
The proc_sys_reset module implements a reset scheme. Input to the proc_sys_reset core is
generated by PS Proc_sys_reset_1_N. The polarity of input reset to this block is indicated by
parameter C_EXT_RESET_HIGH. In this design, C_EXT_RESET_HIGH is set to 0 as reset
generated by PS is active-Low. This block generates various types of resets, such as reset for
interconnect, peripheral reset, and so on. All the blocks in the PL are driven by interconnect
reset, which is active-Low in polarity.
For detailed information about the complete feature set and a functional description of the
proc_sys_reset IP, see the LogiCORE IP Processor System Reset Module Product Specification
(PG164) [Ref 3].
AXI Interconnect
Instances: system_top_i/axi4_hp0, system_top_i/axi4_hp2, system_top_i/axi4_gp0
FPGA logic design has two interconnects for AXI memory-mapped masters and one
interconnect for the AXI register interface.
Zynq-7000 AP SoC ZC702 Base TRD
UG925 (v6.0) February 21, 2014
Frequency (MHz) Phase Buffered
148.5 0
75 0
150 0
75 0
148.5 0
148.5 0
150 0
150 0
75 0
150 0
75 0
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Hardware Architecture
Connection
Yes video_clk_int
Yes clk_75mhz
Yes clk_150mhz
Yes clk_75mhz
Yes fmc_imageon_hdmi_in_0_clk_pin
Yes video_clk_int
Yes clk_150mhz
Yes clk_150mhz
Yes clk_75mhz
clk_150mhz
Yes
Yes clk_75mhz
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