Xilinx Zynq-7000 User Manual page 29

The ADV7511 HDMI transmitter is driven by the logiCVC display controller. Its video input
interface consists of a video clock, a 16-bit video data bus, a data enable, and horizontal
and vertical sync signals. The HDMI transmitter serializes the incoming video stream and
sends it to the display via HDMI. The video input format is YCbCr 4:2:2; built-in color space
converter and chroma resampler are used to drive RGB 4:4:4 on the output side interfacing
the display. The SPDIF pin for audio is unused and therefore not connected in this design.
The interrupt pin is connected to the GIC and the signal is routed through the PL. The main
purpose is to detect if a display is connected to the HDMI port or not; this feature is called
hot plug detect (HPD). Furthermore, the ADV7511 is used to query the Extended Display
Identification Data (EDID), a standard published by the Video Electronics Standards
Association (VESA). The main purpose of the EDID is to provide information on the video
resolutions supported by a video sink, in this case a display monitor. This information is
communicated back to the display controller which then uses the information to generate
the proper timing signals to drive the HDMI transmitter which in turn drives the display.
The FMC standard defines an I2C bus interface to optionally support the Intelligent
Platform Management Interface (IPMI). The Field Replaceable Unit (FRU) for IPMI is a data
structure stored inside the CAT24C02 2 Kb EEPROM of the FMC-IMAGEON daughter card. It
holds the inventory information, such as vendor ID and manufacturer, part number, version
number etc. The reference design tries to access the FRU information to detect the presence
of and to identify the FMC-IMAGEON daughter card.
The ADV7611 HDMI receiver on the FMC-IMAGEON daughter card is used to connect an
external video source like an HD camera or video player via HDMI. The interface to the PL
consists of a video clock and a 16-bit video data bus. The video format interfacing the PL is
YCbCr 4:2:2 with embedded sync signals (i.e. there are no separate signals for data enable,
horizontal and vertical sync to reduce pin count). The SPDIF pin for audio is unused in this
design and hence not connected. The active-low reset and HPD control pins are inputs,
connected to the I/O expander.
The PCA9534 I/O expander is used to drive the reset line and HPD control pin of the
ADV7611 HDMI receiver. The HPD signal is only asserted after the EDID has been
programmed into the internal EEPROM of the ADV7611. On the video input side, the EDID
is used to advertise the video resolutions supported by the HDMI receiver to the video
source (e.g. an HD media player). The video source will receive the HPD event and then
determine the video output resolution based on the EDID information read from the
ADV7611 HDMI receiver. Some video sources do not attempt to read the EDID and
therefore allow driving a potentially unsupported video resolution.
Note that more complex ICs like the ADV7511 or the ADV7611 can also have internal I2C
bus structures to communicate with sub-components (e.g., the ADV7611 is comprised of 7
I2C sub-devices with the EDID EEPROM being one of them).
Zynq-7000 AP SoC ZC702 Base TRD
UG925 (v6.0) February 21, 2014
www.xilinx.com
Hardware Architecture
29
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