Xilinx Zynq-7000 User Manual page 28

X-Ref Target - Figure 2-2
ZC702
SI570
(0x5D)
The PS I2C0 controller is connected via hard-wired MIO signals (SCL on MIO[50] and SDA on
MIO[51]) to an 8-channel I2C multiplexer (PCA9548) at address 0x74 on the ZC702 board.
The following I2C clients are connected to the I2C multiplexer and used in this design: A
programmable clock synthesizer (SI570) is connected to channel 0 at address 0x5D; an
HDMI encoder/transmitter (ADV7511) is connected to channel 1 at address 0x39; and,
optionally, a 2 Kb EEPROM (CAT24C02) is connected to channel 6 at address 0x50 on a
daughter card plugged into the FMC2 slot.
The PS I2C1 controller is connected through the PL via EMIO signals to a 4-channel I2C
multiplexer (PCA9546) at address 0x70 on the FMC-IMAGEON daughter card (if present).
The following I2C clients are connected to the I2C multiplexer and (optionally) used in this
design: An HDMI decoder/receiver (ADV7611) is connected to channel 2 at address 0x4C;
an 8-bit I/O expander (PCA9534) is connected to channel 3 at address 0x20.
Both I2C multiplexers can be reset individually by toggling their active-low reset line
connected to the PS GPIO controller. The 8-channel I2C multiplexer is connected to
GPIO[13] via MIO; the 4-channel I2C multiplexer is connected to GPIO[60] via EMIO (routed
through the PL).
The SI570 clock synthesizer is used to generate an accurate video clock that is used to drive
the display output. The logiCVC display controller configures the SI570 to generate a
specific video clock frequency based on the selected video resolution (e.g., for 1920x1080
at 60 frames per second [1080p60]), the video clock needs to be set to 148.5 MHz. The
generated clock is a differential clock connected the PL. The same clock is used not only to
drive the display output, but it also connects to the VTC's timing generator which in turn
provides video timing signals to the TPG.
Zynq-7000 AP SoC ZC702 Base TRD
UG925 (v6.0) February 21, 2014
PS 12C0
MIO
FMC-IMAGEON
PCA9548
(0x74)
0 1 2 3 4 5 6 7
ADV7511
(0x39)
Figure 2-2: I2C Sub-system
www.xilinx.com
CAT24C02 ADV7611
(0x50) (0x4C)
Hardware Architecture
PS 12C1
EMIO
PCA9546
(0x70)
0 1 2 3
PCA9534
(0x20)
UG925_c2_11_05091
28
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