Xilinx Zynq-7000 User Manual page 23

AXI memory-mapped interconnects are connected to masters like AXI_VDMA and
logiCVC-ML. Slaves connected to these interconnects includes HP0 and HP2 ports of
Zynq-7000 AP SoC PS. This interconnect operates at 150
wide. The read/write acceptance and issuance are set to 8. The acceptance and issuance
helps improve system performance. The PS HP port can accept a maximum burst length of
16. This imposes a limitation on getting minimum acceptable bandwidth for every master in
a multi-master system. The optimum setting of issuance and acceptance reduces throttle
on the bus and compensates for long latencies.
The AXI register interface is clocked at 75
master on this interconnect and connected slaves have register maps. AXI TPG and VTC are
examples of slaves connected to this interconnect. The operations of the video pipeline are
controlled by registers inside every IP. Depending upon data flow required in the video
pipeline, the processor writes these registers through the AXI Lite interconnect. The AXI Lite
interconnect accepts write or read transfers from the CPU, performs address decoding,
selects a particular slave, and establishes a communication channel between the CPU and
the slave device.
For detailed information about the complete feature set and a functional description of the
AXI Interconnect IP, see the LogiCORE IP AXI Interconnect (PG059)
AXI Video Direct Memory Access
Instances: system_top_i/Video_Capture/TPG_VDMA,
system_top_i/Video_Processing/FILTER_VDMA
AXI VDMA has an AXI streaming interface on one side and an AXI memory-mapped
interface on the other side. The VDMA has two channels: MM2S (memory-mapped to
streaming) and S2MM (streaming to memory-mapped). The MM2S channel reads the
number of data beats programmed through the C_MM2S_MAX_BURST_LENGTH parameter
and presents it to the slave device connected through the streaming interface. The data
width of the streaming interface can be different than the memory-mapped interface and
controlled through C_M_AXIS_MM2S_TDATA_WIDTH. The data width of the S2MM
memory-mapped interface is controlled by the C_M_AXI_MM2S_DATA_WIDTH parameter.
The S2MM channel receives data from the master device connected through the streaming
interface. The C_S_AXIS_S2MM_TDATA_WIDTH parameter decides the width of the
streaming interface. Data received on the streaming interface is then written into the
system memory through the memory-mapped interface. The C_M_AXI_S2MM_DATA_WIDTH
parameter decides the data width of the memory-mapped interface and
C_S2MM_MAX_BURST_LENGTH governs the burst length of the write transaction.
In this design, the streaming interface data width is set to 32-bit wide and the
memory-mapped interface is configured as 64-bit wide. The AXI VDMA is used in simple
register direct mode, which removes the area cost of the scatter/gather feature.
Initialization, status, and management registers in the AXI VDMA core are accessed through
an AXI4-Lite slave interface. To get the best possible throughput for AXI VDMA instances,
Zynq-7000 AP SoC ZC702 Base TRD
UG925 (v6.0) February 21, 2014
. The Zynq-7000 AP SoC PS GP0 port acts as
MHz
www.xilinx.com
Hardware Architecture
and the data width is 64-bit
MHz
[Ref 4].
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