Xilinx Zynq-7000 User Manual page 16

This system is implemented in a Zynq-7000 AP SoC device (XC7Z020-CLG484-1) using
Vivado® Design Suite, version 2013.3 tools.
The PL hardware utilization for the implemented design is shown in
Table 2-1: PL Hardware Utilization for Device XC7Z020-CLG484-1
FPGA Components
LUTs
I/Os
Slice registers
FPGA Logic Memory
RAMB36/FIFO
RAMB18
Notes:
1. The figures provided here are only indicative of nature and can vary between different tool chain versions.
The PL-implemented video IP and custom logic address map is shown in
Table 2-2: FPGA Logic Address Map for the Zynq-7000 AP SoC ZC702 Base TRD
Instance
system_top_i/VTC_0
TPG_0
TPG_VDMA
FILTER_VDMA
LOGICVC_0
PERF_MON_HP0_HP2
CRESAMPLE_0
YUV2RGB_0
FILTER_ENGINE
System Configuration
Processing System
This design makes full use of these four major components in the PS:
• Application processor unit (APU)
• Interconnect
• Input/output peripherals (IOP)
• Memory interfaces
Zynq-7000 AP SoC ZC702 Base TRD
UG925 (v6.0) February 21, 2014
Total Available
53,200
200
106,400
140
280
Peripheral
axi_vtc
axi_tpg
axi_vdma
axi_vdma
LogiCVC
axi_perf_mon
v_cresample
v_ycrcb2rgb
sobel_filter_top
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Hardware Architecture
Table 2-1.
(1)
Used
20,992
43
28,212
45
14
Table
Base Address High Address
0x40070000 0x4007FFFF
0x40080000 0x4008FFFF
0x40090000 0x4009FFFF
0x400B0000 0x400BFFFF
0x40030000 0x4003FFFF
0x400F0000 0x400FFFFF
0x40040000 0x4004FFFF
0x40050000 0x4005FFFF
0x400D0000 0x400DFFFF
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% Used
39
21
26
32
5
2-2.
16