Xilinx Zynq-7000 User Manual page 17

This section describes some of the features of the PS used in this design. For detailed
information about the complete feature set including a functional description, see the
Zynq-7000 All Programmable SoC Technical Reference Manual (UG585)
APU
The APU includes the dual ARM Cortex-A9 core processor, snoop control unit (SCU), L2
cache controller, on-chip memory (OCM), 8-channel DMA, system watchdog timer (SWDT),
and triple-timer controller (TTC) blocks.
Cortex-A9 Core - The ARM Cortex-A9 core processor implements the ARMv7 architecture
and runs 32-bit ARM instructions, 16-bit and 32-bit Thumb instructions, and 8-bit Java byte
codes in the Jazelle state. The media processing engine implements ARM NEON
coprocessor technology, a single instruction multiple data (SIMD) architecture that adds
instructions targeted at audio, video, 3D graphics, image, and speech processing. For this
TRD, both ARM cores run at 667 MHz.
General Interrupt Controller - The GIC collects interrupts from various sources and
distributes these interrupts to each of the ARM cores. The interrupt distributor holds the list
of pending interrupts for each ARM Cortex-A9 core processor and then selects the highest
priority interrupt before issuing it to the Cortex-A9 processor interface. Interrupts of equal
priority are resolved by selecting the lowest ID. A total of 64 shared peripheral interrupts (PL
interrupts + PS I/O peripheral interrupts) are supported, starting from ID 32.
interrupt IDs for interrupts coming from PL.
Table 2-3: Interrupt IDs for PL-Generated Interrupts
Interrupt line
CVC_DISPLAY_interrupt
TPG_VDMA_s2mm_introut
FIILTER_VDMA_s2mm_introut
FIILTER_VDMA_mm2s_introut
FILTER_0_interrupt
ADV7511 HPD interrupt
Interconnect
The interconnect unit connects all PS and PL master and slave devices. There are a total of
six Advanced eXtensible Interface (AXI) slave ports dedicated for AXI masters residing in the
PL, and four of these ports contain deep FIFOs to improve data throughput. Two AXI master
ports provide access to AXI slaves in the PL. In this design, masters in PL are connected
through two AXI slave ports with deep FIFOs. One AXI master port is used to access
registers in AXI slave IPs in PL.
An advanced peripheral bus (APB) master port is provided for accessing software
programmable registers of all PS modules. The top level switch is AXI3-compliant, the soft
Zynq-7000 AP SoC ZC702 Base TRD
UG925 (v6.0) February 21, 2014
ID Type
91 Level
90 Level
89 Level
88 Level
87 Level
86 Level
www.xilinx.com
Hardware Architecture
[Ref 2].
Table 2-3 lists
Instance
CVC_DISPLAY
TPG_VDMA
FIILTER_VDMA
FIILTER_VDMA
FILTER_ENGINE
HDMI_O_INT
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