Xilinx Zynq-7000 User Manual page 19

other AXI masters. In this design, DDR3 is configured to run at 533 MHz, and the AXI
interface is running at 355 MHz.
PL Clocks
The PS provides four fully programmable clocks (FCLK_CLK) to the PL. These clocks are
routed directly to PL clock buffers to serve as a frequency source for the PL. The clock
generator module in PL gets a 100 MHz clock from FCLK_CLK0.
PL Reset
The PS provides four FCLK_RESET[3:0]_N fully programmable reset signals to the PL. These
signals are asynchronous to PS clocks. The PL logic reset block in this design receives input
from FCLK_RESET0_N and generates necessary reset signals for the design implemented in
PL.
Programmable Logic
Clocking
The FPGA logic design has three clock domains: AXI MM (memory-mapped) interconnect,
AXI register interface, and video clock. These domains run at 150 MHz, 75 MHz, and
148.5 MHz, respectively.
The clock generator module receives a 100 MHz input clock from the PS FCLK_CLK0 and
generates 75 MHz and 150 MHz. The AXI Lite interconnect works on 75 MHz. Apart from
the AXI Lite interconnect, the register interface of AXI VDMA, AXI TPG, logiCVC-ML, VTC,
and perf_monitor are driven by the 75 MHz clock.
Two instances of the AXI_MM interconnect connected to the HP port of the PS run on
150 MHz. The S2MM (stream to memory map) and MM2S (memory map to stream)
channels of VDMAs are running at 150 MHz. The 150 MHz clock drives the logiCVC-ML
memory read interface and also the AXI slave interface of the Sobel filter.
The video clock comes from the onboard clock synthesizer or the FMC-IMAGEON card.
BUFGMUX dynamically selects which video clock source drives logic running on the video
clock domain. The VTC, VID_IN_AXI4S, and logiCVC-ML blocks run on the video clock.
Table 2-5 lists system clocks.
Zynq-7000 AP SoC ZC702 Base TRD
UG925 (v6.0) February 21, 2014
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Hardware Architecture
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