Xilinx Zynq-7000 User Manual page 25

and height of the pattern is equal to 1920 x 1080, selected through the line length and
frame height register.
For detailed information on the complete feature set and a functional description of Test
Pattern Generator, see the LogiCORE IP Test Pattern Generator Product Guide (PG103)
logiCVC-ML
Instance: system_top_i/Video_Display/LOGICVC_0
The logiCVC-ML is a multi-layer video display controller from Xylon
(www.logicbricks.com/Products/logiCVC-ML.aspx). The logiCVC-ML controller refreshes the
display image by reading the video memory and converting the read data into a data
stream acceptable for the display interface. It generates control signals for the display, and
supports multiple layers with video processing functions such as alpha blending,
transparency, and move around.
For detailed information about the complete feature set, a functional description, and
license information for logiCVC-ML IP, refer to the Xylon data sheet
(www.logicbricks.com/Products/logiCVC-ML.aspx).
AXI Performance Monitor
Instance: system_top_i/PERF_MON_HP0_HP2
The AXI Performance Monitor can monitor and analyze system behavior on the AXI
interface. This core is used in the Base TRD to measure read and write throughput on AXI
slave ports of the PS (HP0 and HP2), which are used to access DDR memory from PL. The
core consists of the AXI4-Lite interface to configure and control the core.
This core is configured to measure the read and write throughput by counting the number
of transactions per second. When the configured time interval expires, measured
throughput in bytes is loaded into a register and read by the software application.
Two slots of AXI Performance Monitors are used to measure read and write throughput of
HP0 and HP2 simultaneously.
For detailed information on the complete feature set and a functional description of AXI
Performance Monitor, see the LogiCORE IP AXI Performance Monitor Product Guide (PG037)
[Ref 8].
fmc imageon hdmi in
Instance: system_top_i/HDMI_IN
This IP core receives video from FMC-IMAGEON, in YCrCb 4:2:2 format, with embedded
vblank and hblank signals, and extracts blanking information.
Zynq-7000 AP SoC ZC702 Base TRD
UG925 (v6.0) February 21, 2014
www.xilinx.com
Hardware Architecture
[Ref 7].
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